Jianlei Yang

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 79

Top Topics

Bayesian Inference

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (3) (2024)
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. CoRR (2024)
Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu
Architectural Implications of GNN Aggregation Programming Abstractions. IEEE Comput. Archit. Lett. 23 (1) (2024)
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. CoRR (2024)
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. CoRR (2024)
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory. CoRR (2023)
Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu
Architectural Implications of GNN Aggregation Programming Abstractions. CoRR (2023)
Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Junyi Chen, Lingkun Long, Han Wan, Bei Yu, Weisheng Zhao
TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices. CoRR (2023)
Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. DAC (2023)
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. Sci. China Inf. Sci. 66 (4) (2023)
Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang
) Post-training Model Size Compression. ICCV (2023)
Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao
IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. CoRR (2023)
Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang
) Post-training Model Size Compression. CoRR (2023)
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform. CoRR (2022)
Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang
Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration. CoRR (2022)
Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao
Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. IEEE Trans. Computers 71 (6) (2022)
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. IEEE Trans. Computers 71 (10) (2022)
Han Wan, Hongzhen Luo, Zihao Zhong, Jianlei Yang
Exploring the Factors of Students' Online Learning Based On Structural Equation Modeling. TALE (2022)
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. DAC (2022)
Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Jianlei Yang, Xiaopeng Gao, Weisheng Zhao
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. CoRR (2022)
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. RTAS (2021)
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. CoRR (2021)
Xiaoyi Wang, Shaobin Ma, Sheldon X.-D. Tan, Chase Cook, Liang Chen, Jianlei Yang, Wenjian Yu
Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (3) (2021)
Xin Guo, Jianlei Yang, Haoyi Zhou, Xucheng Ye, Jianxin Li
RoSearch: Search for Robust Student Architectures When Distilling Pre-trained Language Models. CoRR (2021)
Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. CIKM (2021)
Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao
S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. CoRR (2021)
Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. CoRR (2021)
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. IEEE Trans. Neural Networks Learn. Syst. 32 (4) (2021)
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. CoRR (2021)
Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang
TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework with Anonymized Intermediate Representations. CoRR (2020)
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. CoRR (2020)
Jianlei Yang, Yixiao Duan, Tong Qiao, Huanyu Zhou, Jingyuan Wang, Weisheng Zhao
Prototyping federated learning on edge computing systems. Frontiers Comput. Sci. 14 (6) (2020)
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. DAC (2020)
Xucheng Ye, Pengcheng Dai, Junyu Luo, Xin Guo, Yingjie Qi, Jianlei Yang, Yiran Chen
Accelerating CNN Training by Pruning Activation Gradients. ECCV (25) (2020)
Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. CCF Trans. High Perform. Comput. 2 (3) (2020)
Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang
TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework for Deep Learning with Anonymized Intermediate Representations. KDD (2020)
Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. DAC (2020)
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. CoRR (2020)
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques. ACM J. Emerg. Technol. Comput. Syst. 16 (4) (2020)
Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, Weisheng Zhao
Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method. ISCAS (2020)
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques. CoRR (2020)
Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. CoRR (2020)
Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang
Dual-Plane Switch Architecture for Time-Triggered Ethernet. ACM Great Lakes Symposium on VLSI (2020)
Jianlei Yang, Xiaopeng Gao, Weisheng Zhao
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. ACM Great Lakes Symposium on VLSI (2020)
Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao
SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing. ISCAS (2019)
Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. DAC (2019)
Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (1) (2019)
Zirui Xu, Zhao Yang, Jinjun Xiong, Jianlei Yang, Xiang Chen
ELFISH: Resource-Aware Federated Learning on Heterogeneous Edge Devices. CoRR (2019)
Xucheng Ye, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
Accelerating CNN Training by Sparsifying Activation Gradients. CoRR (2019)
Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. ISVLSI (2019)
Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing. CoRR (2019)
Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. Sustain. Comput. Informatics Syst. 22 (2019)
Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao
Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface. ISCAS (2019)
Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. CoRR (2019)
Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. CoRR (2018)
Xufeng Li, Jianlei Yang, Richong Zhang, Hongyuan Ma
A Novel Approach on Entity Linking for Encyclopedia Infoboxes. CCKS (2018)
Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao
Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation. CoRR (2018)
Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao
Spintronics based stochastic computing for efficient Bayesian inference system. ASP-DAC (2018)
Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. FPT (2018)
Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. J. Comput. Sci. Technol. 33 (5) (2018)
Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. ICCAD (2017)
Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang
Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. TrustCom/BigDataSE/ICESS (2017)
Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Li, Weisheng Zhao
Spintronics based Stochastic Computing for Efficient Bayesian Inference System. CoRR (2017)
Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang
Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. ICCD (2017)
Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi
Generative adversarial network based scalable on-chip noise sensor placement. SoCC (2017)
You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao
A novel circuit design of true random number generator using magnetic tunnel junction. NANOARCH (2016)
Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li
Spintronic Memristor as Interface Between DNA and Solid State Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. ACM Great Lakes Symposium on VLSI (2016)
Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. IEEE Trans. Reliab. 65 (4) (2016)
Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. ICCAD (2016)
Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li
A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. ISVLSI (2016)
Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (3) (2016)
Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai
Early stage real-time SoC power estimation using RTL instrumentation. ASP-DAC (2015)
Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li
An overview on memristor crossabr based neuromorphic circuit and architecture. VLSI-SoC (2015)
Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. ACM Great Lakes Symposium on VLSI (2015)
Wei Zhao, Yici Cai, Jianlei Yang
Fast vectorless power grid verification using maximum voltage drop location estimation. ASP-DAC (2014)
Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou
Power supply noise aware evaluation framework for side channel attacks and countermeasures. FPT (2014)
Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Wei Zhao, Yici Cai, Jianlei Yang
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. ASP-DAC (2013)
Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
Selected inversion for vectorless power grid verification by exploiting locality. ICCD (2013)
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
PowerRush : Efficient transient simulation for power grid analysis. ICCAD (2012)
Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
Fast poisson solver preconditioned method for robust power grid analysis. ICCAD (2011)
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
PowerRush: A linear simulator for power grid. ICCAD (2011)
Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI (2011)