Weitao Pan

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 32

Top Topics

Fpga Implementation

Classification Algorithm

Top Venues

Comput. Networks

Publications

Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (3) (2024)
Zhe Zhao, Zhiliang Qiu, Weitao Pan, Hui Li, Ling Zheng, Ya Gao
Design and implementation of a frame preemption model without guard bands for time-sensitive networking. Comput. Networks 243 (2024)
Weitao Pan, Hironori Washizaki, Nobukazu Yoshioka, Yoshiaki Fukazawa, Foutse Khomh, Yann-Gaël Guéhéneuc
A Machine Learning Based Approach to Detect Machine Learning Design Patterns. APSEC (2023)
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory. CoRR (2023)
Weitao Pan, Meng Dong, Cong Wen, Hongjin Liu, Shaolin Zhang, Bo Shi, Zhixiong Di, Zhiliang Qiu, Yiming Gao, Ling Zheng
A unioned graph neural network based hardware Trojan node detection. IEICE Electron. Express 20 (13) (2023)
Zhe Zhao, Lu Gao, Weitao Pan, Zhiliang Qiu, Xu Guo, Ya Gao, Ling Zheng
Access mechanism for period flows of non-deterministic end systems for time-sensitive networks. Comput. Networks 231 (2023)
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform. CoRR (2022)
Meng Dong, Weitao Pan, Zhiliang Qiu, Xiaoxin Qi, Ling Zheng, Huan Liu
A Universal, Low-Delay, SEC-DEC-TAEC Code for State Register Protection. IEEE Access 10 (2022)
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. DAC (2022)
Lei Mao, Zhongyong Liu, Derek Low, Weitao Pan, Qingbo He, Lisa M. Jackson, Qiang Wu
Evaluation Method for Feature Selection in Proton Exchange Membrane Fuel Cell Fault Diagnosis. IEEE Trans. Ind. Electron. 69 (5) (2022)
Ling Zheng, Chen Yi, Weitao Pan, Huan Liu
Combined Shared-Memory and Buffered-Crossbar Architecture for High-Bandwidth Onboard Switching Fabric. APNet (2021)
Jiangyi Shi, Xinyuan Zhang, Peijun Ma, Weitao Pan, Pengfei Li, Zhengguang Tang
Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Jialu Mang, Zhiliang Qiu, Weitao Pan, Meng Dong, Min Wu
GGTS: FPGA-Based General Ground Test System for Space-Borne Equipment. ICCCS (2021)
Jinjian Huang, Zhiliang Qiu, Weitao Pan, Jun Li, Zhikai Gao, Bing Han, Zihao Xiong, Meng Dong
Design of HIMAC Coprocessor for HINOC3.0. ICCCS (2021)
Huan Liu, Zhiliang Qiu, Weitao Pan, Jiajun Li, Jinjian Huang
HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC. APNet (2021)
Huan Liu, Zhiliang Qiu, Weitao Pan, Jun Li, Ling Zheng, Ya Gao
Low-Cost and Programmable CRC Implementation Based on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Jinlong Dong, Zhiliang Qiu, Weitao Pan, Min Wu, Jialiang Cao
Design and Implementation of AS6802 Clock Synchronization System in TTE thernet. ICCCS (2021)
Ling Zheng, Weitao Pan, Ya Gao, Huan Liu, Jing Jiang
Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric. Comput. Networks 198 (2021)
Ling Zheng, Jing Jiang, Weitao Pan, Huan Liu
High-Performance and Range-Supported Packet Classification Algorithm for Network Security Systems in SDN. ICC Workshops (2020)
Ling Zheng, Weitao Pan, Yinghua Li, Ya Gao
Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches. Int. J. Commun. Syst. 33 (8) (2020)
Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang
Dual-Plane Switch Architecture for Time-Triggered Ethernet. ACM Great Lakes Symposium on VLSI (2020)
Ling Zheng, Zhiliang Qiu, Weina Wang, Weitao Pan, Shiyong Sun, Ya Gao
AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation. J. Circuits Syst. Comput. 28 (14) (2019)
Zhiliang Qiu, Weina Wang, Shiyong Sun, Weitao Pan, Ling Zheng, Ya Gao, Zhiyi Zhang
The High Speed Packet Classification Supporting Multi - Field for Flow Tables in OpenFlow. CITS (2018)
Weitao Pan, Lili Gao, Ling Zheng, Zhiliang Qiu, Junxiang Zhang, Dong Zhang, Ya Gao
Research on Model of Five-level Scheduling Based on SDN. CITS (2018)
Ling Zheng, Zhiliang Qiu, Weitao Pan, Yibo Mei, Shiyong Sun, Zhiyi Zhang
Analysis and Implementation of a QoS Optimization Method for Access Networks. IEICE Trans. Commun. (9) (2018)
Ling Zheng, Zhiliang Qiu, Weitao Pan, Ya Gao
A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers. ChinaCom (2018)
Ling Zheng, Zhiliang Qiu, Weitao Pan, Ya Gao, Junxiang Zhang, Dong Zhang
Analysis of a Shared-Private Buffer Management Scheme for Shared Memory Switches. CITS (2018)
Meng Dong, Zhiliang Qiu, Weitao Pan, Can Chen, Junxiang Zhang, Dong Zhang
The Design and Implementation of IEEE 1588v2 Clock Synchronization System by Generating Hardware Timestamps in MAC Layer. CITS (2018)
Ling Zheng, Zhiliang Qiu, Shiyong Sun, Weitao Pan, Ya Gao, Zhiyi Zhang
Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers. J. Commun. Networks 20 (6) (2018)
Ya Gao, Weitao Pan, Ling Zheng
Analyzing the Impact of Redundant Paths on Multistage Switch Performance. ChinaCom (1) (2017)
Ya Gao, Weitao Pan, Ling Zheng
Improved analytical model for performance evaluation of crosspoint-queued switch under uniform traffic. IET Networks 6 (4) (2017)
Hao Shu, Jiangyi Shi, Peijun Ma, Huaxi Gu, Weitao Pan, Lin-An Yang
Dual priority congestion aware shared-resource Network-on-Chip architecture. IEICE Electron. Express 13 (7) (2016)