Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches.
Ling ZhengWeitao PanYinghua LiYa GaoPublished in: Int. J. Commun. Syst. (2020)
Keyphrases
- hardware implementation
- parallel architecture
- shared memory
- buffer management
- distributed memory
- replacement policy
- multithreading
- signal processing
- coarse grained
- efficient implementation
- message passing
- parallel algorithm
- parallel computers
- parallel computing
- flash memory
- real time database systems
- storage management
- memory management
- database systems
- field programmable gate array
- dynamic programming
- parallel machines
- parallel implementation
- highly efficient
- file system
- distributed environment
- network traffic
- image processing
- virtual memory