Sign in
Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers.
Ling Zheng
Zhiliang Qiu
Shiyong Sun
Weitao Pan
Ya Gao
Zhiyi Zhang
Published in:
J. Commun. Networks (2018)
Keyphrases
</>
high speed
detailed design
design process
management system
software architecture
data analysis
hardware design
architectural design
packet switched
low cost
design principles
low power
distributed architecture
design goals
memory hierarchy