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Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.
Wei Wang
Vasilis F. Pavlidis
Yuanqing Cheng
Published in:
ACM Great Lakes Symposium on VLSI (2020)
Keyphrases
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peer to peer
network structure
network traffic
network model
spanning tree
neural network
control system
high speed
network management
heterogeneous networks
square error