Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.

Wei Wang Vasilis F. Pavlidis Yuanqing Cheng

Published in: ACM Great Lakes Symposium on VLSI (2020)

Keyphrases

peer to peer
network structure
network traffic
network model
spanning tree
neural network
control system
high speed
network management
heterogeneous networks
square error