Nadine Azémard

Publication Activity (10 Years)

Years Active: 1991-2023
Publications (10 Years): 8

Top Topics

Wearable Sensors

International Program Committee

Scientific Articles

Randomly Selected

Top Venues

J. Low Power Electron.

Publications

Corentin Delacour, Stefania Carapezzi, Gabriele Boschetto, Madeleine Abernot, Thierry Gil, Nadine Azémard, Aida Todri-Sanial
A mixed-signal oscillatory neural network for scalable analog computations in phase domain. Neuromorph. Comput. Eng. 3 (3) (2023)
Corentin Delacour, Stefania Carapezzi, Madeleine Abernot, Gabriele Boschetto, Nadine Azémard, Jérémie Salles, Thierry Gil, Aida Todri-Sanial
Oscillatory Neural Networks for Edge AI Computing. ISVLSI (2021)
Gwenael Chaillou, Philippe Maurine, Jean Marc Gallière, Nadine Azémard
Iterative Method for Performance Prediction Improvement of Integrated Circuits. DCIS (2021)
Abhishek Singh Dahiya, Jerome Thireau, Jamila Boudaden, Swatchith Lal, Umair Gulzar, Yan Zhang, Thierry Gil, Nadine Azémard, Peter Ramm, Tim Kiessling, Cian O'Murchu, Fredrik Sebelius, Jonas Tilly, Colm Glynn, Shane Geary, Colm O'Dwyer, Kafil Razeeb, Alain Lacampagne, Benoît Charlot, Aida Todri-Sanial
Energy Autonomous Wearable Sensors for Smart Healthcare: A Review. CoRR (2019)
Rida Kheirallah, Jean Marc Gallière, Nadine Azémard, Gilles R. Ducharme
Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. PATMOS (2018)
Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azémard, Aida Todri-Sanial
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic. ICRC (2017)
Ricardo Reis, Nadine Azémard
Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015. J. Low Power Electron. 12 (1) (2016)
Rida Kheirallah, Gilles R. Ducharme, Nadine Azémard
Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices. J. Low Power Electron. 12 (1) (2016)
Nadine Azémard, Eugeni García-Moreno
Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014. J. Low Power Electron. 11 (2) (2015)
Nadine Azémard, Jörg Henkel
Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013. J. Low Power Electron. 10 (1) (2014)
Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
Delay-correlation-aware SSTA based on conditional moments. Microelectron. J. 43 (4) (2012)
Nadine Azémard, Gilles Jacquemod
Selected Articles from the VARI 2012 Workshop. J. Low Power Electron. 8 (5) (2012)
Nadine Azémard, Marc Belleville
Selected Articles from the VARI 2011 Workshop. J. Low Power Electron. 8 (1) (2012)
Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
Statistical timing characterization. ISSoC (2012)
Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. 42 (5) (2011)
Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson
On-Chip Process Variability Monitoring Flow. J. Low Power Electron. 6 (4) (2010)
Nadine Azémard
Selected Peer-Reviewed Articles from the VARI 2010 Workshop. J. Low Power Electron. 6 (4) (2010)
Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
Interpreting SSTA Results with Correlation. PATMOS (2009)
Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS (2009)
V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine
Timing margin evaluation with a simple statistical timing analysis flow. J. Embed. Comput. 3 (3) (2009)
Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels
Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS (2009)
Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
SSTA considering switching process induced correlations. APCCAS (2008)
Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, Philippe Maurine, Nadine Azémard
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI (2008)
Nadine Azémard, Philippe Maurine, Johan Vounckx
Editorial. Integr. 41 (1) (2008)
Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
Low Power Oriented CMOS Circuit Optimization Protocol CoRR (2007)
B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS (2007)
B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
Temperature and voltage aware timing analysis: application to voltage drops. DATE (2007)
Robin Perrot, Nadine Azémard, Philippe Maurine
Request-skip adders : CMOS standard cell data dependent adders. ICECS (2006)
Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integr. 39 (4) (2006)
B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard
Circuit sizing method under delay constraint. ISCAS (2006)
B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
Timing analysis in presence of supply voltage and temperature variations. ISPD (2006)
V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine
Statistical Characterization of Library Timing Performance. PATMOS (2006)
Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
Low Power Oriented CMOS Circuit Optimization Protocol. DATE (2005)
Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard
Speed Indicators for Circuit Optimization. PATMOS (2005)
B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
Temperature Dependency in UDSM Process. PATMOS (2005)
Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard
Circuit optimization based on speed indicators. ICECS (2005)
Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Delay bound based CMOS gate sizing technique. ISCAS (5) (2004)
A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne
Design Optimization with Automated Cell Generation. PATMOS (2004)
Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Performance Metric Based Optimization Protocol. PATMOS (2004)
B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Temperature Dependence in Low Power CMOS UDSM Process. PATMOS (2004)
B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Physical Extension of the Logical Effort Model. PATMOS (2004)
Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
CMOS Gate Sizing under Delay Constraint. PATMOS (2003)
Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne
Metric Definition for Circuit Speed Optimization. PATMOS (2003)
B. Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Continuous representation of the performance of a CMOS library. ESSCIRC (2003)
Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne
Gate speed improvement at minimal power dissipation. APCCAS (2) (2002)
Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne
Transition time modeling in deep submicron CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (11) (2002)
Philippe Maurine, Nadine Azémard, Daniel Auvergne
Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS (2002)
Nadine Azémard, Daniel Auvergne
POPS: A tool for delay/power performance optimization. J. Syst. Archit. 47 (3-4) (2001)
Philippe Maurine, Nadine Azémard, Daniel Auvergne
Gate Sizing for Low Power Design. VLSI-SOC (2001)
Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne
Feasible Delay Bound Definition. VLSI-SOC (2001)
Nadine Azémard, M. Aline, Daniel Auvergne
Delay bound determination for timing closure satisfaction. ISCAS (5) (2001)
S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne
Delay-power performance analysis. ICECS (1999)
S. Turgis, Nadine Azémard, Daniel Auvergne
Design and selection of buffers for minimum power-delay product. ED&TC (1996)
S. Turgis, Nadine Azémard, Daniel Auvergne
Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD (1995)
Nadine Azémard, V. Bonzom, Daniel Auvergne
P.SIZE: a sizing aid for optimized designs. EURO-DAC (1992)
Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert
Formal sizing rules of CMOS circuits. EURO-DAC (1991)