Gate speed improvement at minimal power dissipation.
Philippe MaurineXavier MichelNadine AzémardDaniel AuvergnePublished in: APCCAS (2) (2002)
Keyphrases
- power dissipation
- cmos technology
- power consumption
- nm technology
- low power
- digital signal processing
- low voltage
- network on chip
- high speed
- chip design
- short circuit
- flip flops
- low cost
- power reduction
- finite state machines
- logic circuits
- parallel processing
- machine learning
- control system
- pattern recognition
- case study