Daniel Auvergne

Publication Activity (10 Years)

Years Active: 1985-2007
Publications (10 Years): 0

Publications

Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
Low Power Oriented CMOS Circuit Optimization Protocol CoRR (2007)
B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
Low Power Oriented CMOS Circuit Optimization Protocol. DATE (2005)
Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Delay bound based CMOS gate sizing technique. ISCAS (5) (2004)
A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne
Design Optimization with Automated Cell Generation. PATMOS (2004)
Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Performance Metric Based Optimization Protocol. PATMOS (2004)
B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Temperature Dependence in Low Power CMOS UDSM Process. PATMOS (2004)
B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Physical Extension of the Logical Effort Model. PATMOS (2004)
Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
CMOS Gate Sizing under Delay Constraint. PATMOS (2003)
Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne
Metric Definition for Circuit Speed Optimization. PATMOS (2003)
Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne
Design Techniques for EEPROMs Embedded in Portable Systems on Chips. IEEE Des. Test Comput. 20 (1) (2003)
B. Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne
Continuous representation of the performance of a CMOS library. ESSCIRC (2003)
Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, Daniel Auvergne
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. PATMOS (2002)
Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne
Gate speed improvement at minimal power dissipation. APCCAS (2) (2002)
Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne
Transition time modeling in deep submicron CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (11) (2002)
Philippe Maurine, Nadine Azémard, Daniel Auvergne
Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS (2002)
Fabrice Picot, Philippe Coll, Daniel Auvergne
Crosstalk Measurement Technique for CMOS ICs. PATMOS (2002)
Wenceslas Rahajandraibe, Christian Dufaza, Daniel Auvergne, Bruno Cialdella, Bernard Majoux, Vivek Chowdhury
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. DATE (2002)
Nadine Azémard, Daniel Auvergne
POPS: A tool for delay/power performance optimization. J. Syst. Archit. 47 (3-4) (2001)
Philippe Maurine, Nadine Azémard, Daniel Auvergne
Gate Sizing for Low Power Design. VLSI-SOC (2001)
Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne
Feasible Delay Bound Definition. VLSI-SOC (2001)
Nadine Azémard, M. Aline, Daniel Auvergne
Delay bound determination for timing closure satisfaction. ISCAS (5) (2001)
Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne
Output transition time modeling of CMOS structures. ISCAS (5) (2001)
Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne
Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. PATMOS (2000)
Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne
Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. MTDT (2000)
Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne
Second Generation Delay Model for Submicron CMOS Process. PATMOS (2000)
Fernando Moraes, Michel Robert, Daniel Auvergne
A Virtual CMOS Library Approach for East Layout Synthesis. VLSI (1999)
Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne
RF Interface Design Using Mixed-Mode Methodology. VLSI (1999)
Jean Michel Daga, Daniel Auvergne
A comprehensive delay macro modeling for submicrometer CMOS logics. IEEE J. Solid State Circuits 34 (1) (1999)
S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne
Delay-power performance analysis. ICECS (1999)
S. Turgis, Daniel Auvergne
A novel macromodel for power estimation in CMOS structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (11) (1998)
Jean Michel Daga, E. Ottaviano, Daniel Auvergne
Temperature Effect on Delay for Low Voltage Applications. DATE (1998)
S. Turgis, Jean Michel Daga, Josep M. Portal, Daniel Auvergne
Internal power modelling and minimization in CMOS inverters. ED&TC (1997)
S. Turgis, Nadine Azémard, Daniel Auvergne
Design and selection of buffers for minimum power-delay product. ED&TC (1996)
Denis Deschacht, Christophe Dabrin, Daniel Auvergne
Delay propagation effect in transistor gates. IEEE J. Solid State Circuits 31 (8) (1996)
Jean Michel Daga, Michel Robert, Daniel Auvergne
Delay modelling improvement for low voltage applications. EURO-DAC (1995)
S. Turgis, Nadine Azémard, Daniel Auvergne
Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD (1995)
Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne
Influence of Locig Block Layout Architecture on FPGA Performance. FPL (1994)
Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne
Post-layout timing simulation of CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (8) (1993)
Nadine Azémard, V. Bonzom, Daniel Auvergne
P.SIZE: a sizing aid for optimized designs. EURO-DAC (1992)
D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne
TVA: A timing verifier with analytic temporal modelling. Microprocessing and Microprogramming 32 (1-5) (1991)
Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert
Formal sizing rules of CMOS circuits. EURO-DAC (1991)
Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne
Path runner: an accurate and fast timing analyser. EURO-DAC (1990)
Michel Renovell, Gaston Cambon, Daniel Auvergne
FSPICE: a tool for fault modelling in MOS circuits. Integr. 3 (3) (1985)