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Post-layout timing simulation of CMOS circuits.
Denis Deschacht
Michel Robert
Nadine Azémard-Crestani
Daniel Auvergne
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1993)
Keyphrases
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circuit design
delay insensitive
high speed
analog vlsi
chip design
asynchronous circuits
vlsi circuits
cmos technology
simulation model
low cost
random access memory
mathematical model
real time
simulation study
simulation environment
focal plane