Denis Deschacht

Publication Activity (10 Years)

Years Active: 1990-2010
Publications (10 Years): 0

Publications

Jean-Etienne Lorival, Denis Deschacht
Crosstalk pulsewidth calculation. Microelectron. J. 41 (8) (2010)
Denis Deschacht
DSM interconnects: importance of inductance effects and corresponding range of length. IEEE Trans. Very Large Scale Integr. Syst. 14 (7) (2006)
Denis Deschacht, Alain Lopez
Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation. VLSI Design (2005)
Alain Lopez, Denis Deschacht
Comparison between Different Data Buses Configurations. ISVLSI (2004)
Grégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret
Impact of Low-K on Crosstalk. ISQED (2002)
Denis Deschacht, Grégory Servel
On-chip interconnections: impact of adjacent lines on timing. ASP-DAC (2001)
Grégory Servel, Denis Deschacht
On-chip crosstalk evaluation between adjacent interconnections. ICECS (2000)
Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis
Theoretical limits for signal reflections due to inductance for on-chip interconnections. SLIP (2000)
Grégory Servel, L. B. Kenmei, Fabrice Huret, Erick Paleczny, Patrick Kennis, Denis Deschacht
Inductance effect for interconnection timing analysis in submicronic circuits. ICECS (1999)
Denis Deschacht, Christophe Dabrin, Daniel Auvergne
Delay propagation effect in transistor gates. IEEE J. Solid State Circuits 31 (8) (1996)
Denis Deschacht, Christophe Dabrin
A new and accurate interconnection delay time evaluation in a general tree-type network. ASP-DAC (1995)
Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne
Post-layout timing simulation of CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (8) (1993)
D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne
TVA: A timing verifier with analytic temporal modelling. Microprocessing and Microprogramming 32 (1-5) (1991)
Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert
Formal sizing rules of CMOS circuits. EURO-DAC (1991)
Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne
Path runner: an accurate and fast timing analyser. EURO-DAC (1990)