CMOS Gate Sizing under Delay Constraint.

Alexandre Verle Xavier Michel Philippe Maurine Nadine Azémard Daniel Auvergne

Published in: PATMOS (2003)

Keyphrases

cmos technology
power dissipation
high speed
power consumption
nm technology
low power
low cost
vlsi circuits
gate dielectrics
data sets
constraint solving
low voltage
real time
global constraints
metal oxide semiconductor