Gate Sizing for Low Power Design.

Philippe Maurine Nadine Azémard Daniel Auvergne

Published in: VLSI-SOC (2001)

Keyphrases

low power
cmos technology
single chip
low cost
low power consumption
vlsi architecture
power consumption
high speed
logic circuits
nm technology
gate array
wireless transmission
power dissipation
digital signal processing
ultra low power
vlsi implementation
high power
power reduction
mixed signal
digital camera