M. Aline

Publication Activity (10 Years)

Years Active: 1999-2003
Publications (10 Years): 0

Publications

E. Kinvi-Boh, M. Aline, Olivier Sentieys, Edgar "Dan" Olson
MVL circuit design and characterization at the transistor level using SUS-LOC. ISMVL (2003)
Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne
Feasible Delay Bound Definition. VLSI-SOC (2001)
Nadine Azémard, M. Aline, Daniel Auvergne
Delay bound determination for timing closure satisfaction. ISCAS (5) (2001)
S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne
Delay-power performance analysis. ICECS (1999)