Delay bound based CMOS gate sizing technique.
Alexandre VerleXavier MichelPhilippe MaurineNadine AzémardDaniel AuvergnePublished in: ISCAS (5) (2004)
Keyphrases
- cmos technology
- power dissipation
- nm technology
- upper bound
- power consumption
- low power
- lower bound
- high speed
- low cost
- gate dielectrics
- circuit design
- worst case
- delay insensitive
- metal oxide semiconductor
- multiple input
- low voltage
- real time
- vc dimension
- analog vlsi
- image sensor
- power supply
- critical path
- genetic algorithm
- neural network