Jean Marc Gallière

Publication Activity (10 Years)

Years Active: 2001-2022
Publications (10 Years): 18

Top Topics

Defect Detection

Comparative Study

Phase Information

Analytical Model

Top Venues

J. Electron. Test.

Publications

G. Chancel, Jean Marc Gallière, Philippe Maurine
Body Biasing Injection: To Thin or Not to Thin the Substrate? COSADE (2022)
G. Chancel, Jean Marc Gallière, Philippe Maurine
Body Biasing Injection: Impact of substrate types on the induced disturbancesƒ. FDTC (2022)
J. Toulemont, G. Chancel, Jean Marc Gallière, Frédérick Mailly, Pascal Nouet, Philippe Maurine
On the scaling of EMFI probes. FDTC (2021)
Gwenael Chaillou, Philippe Maurine, Jean Marc Gallière, Nadine Azémard
Iterative Method for Performance Prediction Improvement of Integrated Circuits. DCIS (2021)
J. Toulemont, N. Ouldei-Tebina, Jean Marc Gallière, Pascal Nouet, E. Bourbao, Philippe Maurine
A Simple Protocol to Compare EMFI Platforms. IACR Cryptol. ePrint Arch. 2020 (2020)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS (2019)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. J. Electron. Test. 35 (1) (2019)
Maxime Cozzi, Jean Marc Gallière, Philippe Maurine
Thermal Scans for Detecting Hardware Trojans. COSADE (2018)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS (2018)
Maxime Cozzi, Jean Marc Gallière, Philippe Maurine
Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection. DSD (2018)
Rida Kheirallah, Jean Marc Gallière, Nadine Azémard, Gilles R. Ducharme
Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. PATMOS (2018)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. 34 (2) (2018)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell, Keshav Singh
Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI (2017)
Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell, Keshav Singh
Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS (2017)
Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. J. Electron. Test. 33 (4) (2017)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
Analysis of short defects in FinFET based logic cells. LATS (2017)
Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS (2016)
Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. ISVLSI (2016)
Jean Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell
Testing for gate oxide short defects using the detectability interval paradigm. it Inf. Technol. 56 (4) (2014)
Jean Marc Gallière, Jerome Boch
A toolkit to demystify CMOS Active Pixel Sensors. MSE (2013)
Jean Marc Gallière, Luigi Dilillo
Versatile march test generator for hands-on memory testing laboratory. MSE (2011)
Luigi Dilillo, Paolo Rech, Jean Marc Gallière, Patrick Girard, Frederic Wrobel, Frédéric Saigné
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. LATW (2011)
Jean Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo
A roaming memory test bench for detecting particle induced SEUs. ITC (2010)
Jean Marc Gallière, Jerome Boch
A mixed TCAD/Electrical simulation laboratory to open up the microelectronics teaching. MSE (2009)
Jean Marc Gallière, Philippe Papet, Laurent Latorre
A 2-D VHDL-AMS Model for Disk-Shape Piezoelectric Transducers. BMAS (2008)
Jean Marc Gallière, Guy Cathébras
Stream Manager, Easy CAD Tools Switching in Academic Context. MSE (2007)
Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS (2005)
Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand
Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20 (2) (2005)
Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium (2003)
Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. 19 (4) (2003)
Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
Modeling gate oxide short defects in CMOS minimum transistors. ETW (2002)
Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW (2001)
Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand
Boolean and current detection of MOS transistor with gate oxide short. ITC (2001)