Víctor H. Champac

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 28

Top Topics

Hilbert Transform

Top Venues

J. Electron. Test.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. J. Electron. Test. 40 (1) (2024)
Leonardo Miceli, Elena Ioana Vatajelu, Víctor H. Champac
Fault Analysis for a MTJ-based Spiking Neural Network. LATS (2024)
Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli
A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. LATS (2023)
Freddy Forero, Víctor H. Champac, Michel Renovell
B-open Defect: A Novel Defect Model in FinFET Technology. ACM J. Emerg. Technol. Comput. Syst. 19 (1) (2023)
Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations. LATS (2022)
Víctor H. Champac, Javier Mesalles, Hector Villacorta, Fabian Vargas
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell. J. Electron. Test. 37 (3) (2021)
Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes, Jose R. Noriega-Luna, A. Vera-Marquina
Identification of Logic Paths Influenced by Severe Coupling Capacitances. J. Electron. Test. 36 (6) (2020)
Zahira Perez, Javier Mesalles, Hector Villacorta, Fabian Vargas, Víctor H. Champac
Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells. LATS (2020)
Freddy Forero, Michel Renovell, Víctor H. Champac
B-open: A New Defect in Nanometer Technologies due to SADP Process. ETS (2019)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS (2019)
Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes, Jose R. Noriega-Luna, A. Vera-Marquina
Identification of Logic Paths Influenced by Severe Coupling Capacitances. LATS (2019)
Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac
Modeling and Detectability of Full Open Gate Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Andres F. Gomez, Víctor H. Champac
An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. J. Electron. Test. 35 (1) (2019)
Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. VLSI-SoC (Selected Papers) (2018)
Andres F. Gomez, Víctor H. Champac
Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects. ACM Trans. Design Autom. Electr. Syst. 23 (3) (2018)
Andres F. Gomez, Freddy Forero, Kaushik Roy, Víctor H. Champac
Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. VLSI-SoC (2018)
Zahira Perez, Hector Villacorta, Víctor H. Champac
An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations. VLSI-SoC (2018)
Andres F. Gomez, Roberto Gómez, Víctor H. Champac
A metric-guided gate-sizing methodology for aging guardband reduction. LATS (2018)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. 34 (2) (2018)
Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac
Analysis of short defects in FinFET based logic cells. LATS (2017)
Andres F. Gomez, Felipe Lavratti, Guilherme Medeiros Machado, M. Sartori, Letícia Maria Veiras Bolzani, Víctor H. Champac, Fabian Vargas
Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. Microelectron. Reliab. 67 (2016)
Hector Villacorta, Jaume Segura, Víctor H. Champac
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. J. Electron. Test. 32 (3) (2016)
Andres F. Gomez, Víctor H. Champac
Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring. IEEE Trans. Very Large Scale Integr. Syst. 24 (7) (2016)
Andres F. Gomez, Víctor H. Champac
Critical path selection under NBTI/PBTI aging for adaptive frequency tuning. EWDTS (2016)
Jesus Moreno, Michel Renovell, Víctor H. Champac
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac
Behavior and test of open-gate defects in FinFET based cells. ETS (2016)
Freddy Forero, Andres F. Gomez, Víctor H. Champac
Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage. J. Low Power Electron. 12 (4) (2016)
Freddy Forero, Andres F. Gomez, Víctor H. Champac
A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage. LATS (2016)
Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez
Circuit performance optimization for local intra-die process variations using a gate selection metric. VLSI-SoC (2015)
Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura, Víctor H. Champac
and body bias conditions for testing bridge defects in the presence of process variations. Microelectron. J. 46 (5) (2015)
Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura, Víctor H. Champac
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. LATS (2015)
Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal
Message from the LATS2015 Chairs. LATS (2015)
Andres F. Gomez, Víctor H. Champac
Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. LATS (2015)
Jose Luis Garcia-Gervacio, Alejandro Nocua, Víctor H. Champac
Screening small-delay defects using inter-path correlation to reduce reliability risk. Microelectron. Reliab. 55 (6) (2015)
Andres F. Gomez, Víctor H. Champac
A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. VLSI-SoC (2015)
Andres F. Gomez, Leticia B. Poehls, Fabian Vargas, Víctor H. Champac
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. VTS (2015)
Jose Luis Garcia-Gervacio, Jaime Martínez-Castillo, Víctor H. Champac
Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. LATW (2014)
C. J. Clark, Víctor H. Champac
Hot topic session 12B: Stay relevant with standards-based DFT. VTS (2014)
Hector Villacorta, Jaume Segura, Sebastià A. Bota, Víctor H. Champac
Analysis of fin height on FinFET SRAM cell hardening. MWSCAS (2014)
Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras
Skew violation verification in digital interconnect signals based on signal addition. IEICE Electron. Express 11 (15) (2014)
Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura, Roberto Gómez
Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. IEEE Des. Test 30 (6) (2013)
Julio César Vázquez, Víctor H. Champac, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. J. Electron. Test. 29 (3) (2013)
Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura
Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. LATW (2013)
Jackson Pachito, Celestino V. Martins, Bruno Jacinto, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. IEEE Des. Test Comput. 29 (5) (2012)
Jesus Moreno, Víctor H. Champac, Michel Renovell
Low voltage testing for interconnect opens under process variations. LATW (2012)
Hector Villacorta, Víctor H. Champac, Sebastià A. Bota, Jaume Segura
and body bias in a delay based test. Microelectron. Reliab. 52 (11) (2012)
Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu
Small-delay defects detection under process variation using Inter-Path Correlation. VTS (2012)
Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barcelo, Roberto Gómez, Chuck Hawkins, Jaume Segura
Testing of Stuck-Open Faults in Nanometer Technologies. IEEE Des. Test Comput. 29 (4) (2012)
Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Letícia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electron. 7 (4) (2011)
Jesus Moreno, Víctor H. Champac, Michel Renovell
A new methodology for realistic open defect detection probability evaluation under process variations. VTS (2011)
Jose Luis Garcia-Gervacio, Víctor H. Champac
Computing the Detection Probability for Small Delay Defects of Nanometer ICs. J. Electron. Test. 27 (6) (2011)
Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. VTS (2011)
Hector Villacorta, Víctor H. Champac, Chuck Hawkins, Jaume Segura
Reliability analysis of small delay defects in vias located in signal paths. LATW (2010)
Jose Luis Garcia-Gervacio, Víctor H. Champac
Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. ETS (2010)
Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Predictive error detection by on-line aging monitoring. IOLTS (2010)
Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Programmable aging sensor for automotive safety-critical applications. DATE (2010)
Víctor H. Champac, Victor Avendaño, Joan Figueras
Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira
Low-sensitivity to process variations aging sensor for automotive safety-critical applications. VTS (2010)
Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS (2009)
Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Built-in aging monitoring for safety-critical applications. IOLTS (2009)
Roberto Gómez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
A modern look at the CMOS stuck-open fault. LATW (2009)
Jose Luis Garcia-Gervacio, Víctor H. Champac
Detectability analysis of small delays due to resistive opens considering process variations. IOLTS (2009)
Nestor Hernandez, Víctor H. Champac
Testing Skew and Logic Faults in SoC Interconnects. ISVLSI (2008)
Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac
A design methodology for logic paths tolerant to local intra-die variations. ISCAS (2008)
Roberto Gómez, Alejandro Girón, Víctor H. Champac
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. J. Electron. Test. 24 (6) (2008)
Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac
Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
Víctor H. Champac, Antonio Zenteno, José L. Garcia
Testing of resistive opens in CMOS latches and flip-flops. ETS (2005)
Roberto Gómez, Alejandro Girón, Víctor H. Champac
Test of Interconnection Opens Considering Coupling Signals. DFT (2005)
Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs
Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium (2004)
Victor Avendaño, Víctor H. Champac, Joan Figueras
Signal integrity verification using high speed monitors. ETS (2004)
Fabian Vargas, Víctor H. Champac
Guest Editorial. J. Electron. Test. 20 (4) (2004)
Victor Avendaño, Víctor H. Champac, Joan Figueras
Signal integrity loss in bus lines due to open shielding defects. ETW (2003)
Víctor H. Champac, Ingrid Jansch-Pôrto
Guest Editorial. J. Electron. Test. 19 (1) (2003)
Antonio Zenteno, Víctor H. Champac, Jaime Ramírez-Angulo
Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory Elements. LATW (2002)
Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac, Alejandro Díaz-Sánchez
A new technique for noise-tolerant pipelined dynamic digital circuits. ISCAS (4) (2002)
Antonio Zenteno, Víctor H. Champac, Joan Figueras
Detectability Conditions of Full Opens in the Interconnections. J. Electron. Test. 17 (2) (2001)
Anotnio Zenteno, Víctor H. Champac, Joan Figueras
Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. LATW (2001)
Antonio Zenteno, Víctor H. Champac
Resistive Opens in a Class of CMOS Latches: Analysis and DFT. VTS (2001)
Víctor H. Champac, Victor Avendaño, Gordana Jovanovic-Dolecek
Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential Amplifier. LATW (2001)
Marcelo Lubaszewski, Víctor H. Champac
Guest Editorial. J. Electron. Test. 17 (2) (2001)
Gordana Jovanovic-Dolecek, Víctor H. Champac
CGTDEMO - educational software for the central limit theorem. ACM SIGCSE Bull. 32 (2) (2000)
Víctor H. Champac, Antonio Zenteno
Detectability Conditions for Interconnection Open Defect. VTS (2000)
Antonio Zenteno, Víctor H. Champac, Joan Figueras
Detectability Dependency on Test Generation Process for Interconnection Opens. LATW (2000)
Víctor H. Champac, José Castillejos, Joan Figueras
IDDQ Testing of Opens in CMOS SRAMs. J. Electron. Test. 15 (1-2) (1999)
Arturo Sarmiento-Reyes, Miguel Ángel Gutiérrez de Anda, Víctor H. Champac
A Graph-Oriented CAD Tool for Establishing the Topological Diagnostic Conditions of Analogue Circuits. SBCCI (1998)
Víctor H. Champac, José Castillejos, Joan Figueras
IDDQ Testing of Opens in CMOS SRAMs. VTS (1998)
Víctor H. Champac, Joan Figueras
Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. VLSI Design 5 (3) (1997)
Víctor H. Champac, Joan Figueras
Testability of floating gate defects in sequential circuits. VTS (1995)
Víctor H. Champac, Antonio Rubio, Joan Figueras
testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (3) (1994)
Víctor H. Champac, Antonio Rubio, Joan Figueras
Analysis of the Floating Gate Defect in CMOS. DFT (1993)
Jaume A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio
Quiescent current analysis and experimentation of defective CMOS circuits. J. Electron. Test. 3 (4) (1992)
Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. ITC (1991)