Isabel C. Teixeira

Publication Activity (10 Years)

Years Active: 1990-2018
Publications (10 Years): 1

Top Topics

Power Reduction

Top Venues

J. Electron. Test.

Publications

Jorge Semião, Ruben Cabral, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Performance Sensor for Reliable Operation. HCI (8) (2018)
Carlos Leong, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling. J. Low Power Electron. 11 (4) (2015)
Carlos Leong, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Fault-tolerance in FPGA focusing power reduction or performance enhancement. LATS (2015)
Jorge Semião, David Saraiva, Carlos Leong, André Romão, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Performance sensor for tolerance and predictive detection of delay-faults. DFT (2014)
Carlos Leong, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas
Aging monitoring with local sensors in FPGA-based designs. FPL (2013)
Julio César Vázquez, Víctor H. Champac, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. J. Electron. Test. 29 (3) (2013)
Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits. J. Electron. Test. 28 (4) (2012)
Jackson Pachito, Celestino V. Martins, Bruno Jacinto, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. IEEE Des. Test Comput. 29 (5) (2012)
Jackson Pachito, Celestino V. Martins, Jorge Semião, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira
The influence of clock-gating on NBTI-induced delay degradation. IOLTS (2012)
R. S. Oliveira, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications. LATW (2011)
R. S. Oliveira, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications. J. Low Power Electron. 7 (4) (2011)
Vasco Bexiga, Carlos Leong, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs. FPL (2011)
Judit Freijedo, María Dolores Valdés, Lucía Costas, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing. J. Low Power Electron. 7 (2) (2011)
Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
Modeling the effect of process variations on the timing response of nanometer digital circuits. LATW (2011)
María Dolores Valdés, Judit Freijedo, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects. LATW (2011)
Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. VTS (2011)
Raul Chipana, Letícia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, João Paulo Teixeira
Investigating the Use of BICS to detect resistive-open defects in SRAMs. IOLTS (2010)
Judit Freijedo, Lucía Costas, Jorge Semião, Juan J. Rodríguez-Andina, María José Moure, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance. J. Low Power Electron. 6 (2) (2010)
Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, J. C. Silva, Pedro Lousã, João Varela
Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems. DDECS (2010)
Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Predictive error detection by on-line aging monitoring. IOLTS (2010)
Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Programmable aging sensor for automotive safety-critical applications. DATE (2010)
Carlos Leong, João Paulo Teixeira, Isabel C. Teixeira, R. Bugalho, Manuel Ferreira, Pedro Miguel Rodrigues, J. C. Silva, Pedro Lousã, João Varela
Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels. ISCAS (2010)
Jorge Semião, Judit Freijedo, Marlon Moraes, M. Mallmann, C. Antunes, Juliano Benfica, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Juan J. Rodríguez-Andina, João Paulo Teixeira, D. Lupi, Edmundo Gatti, L. Garcia, Fernando Hernandez
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment. LATW (2009)
Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
Built-in aging monitoring for safety-critical applications. IOLTS (2009)
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. IOLTS (2009)
Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, Joel Rego, Pedro Neves, Fernando Piedade, Pedro Lousã, Pedro Miguel Rodrigues, Andreia Trindade, R. Bugalho, J. F. Pinheiro, Manuel Ferreira, João Varela
Data Acquisition Electronics for PET Mammography Imaging. BIODEVICES (2009)
Edgar Albuquerque, Vasco Bexiga, Ricardo Bugalho, Bruno Carriço, Cláudia S. Ferreira, Miguel Ferreira, Joaquim Godinho, Fernando M. Gonçalves, Carlos Leong, Pedro Lousã, Pedro Machado, Rui Moura, Pedro Neves, Catarina Ortigão, Fernando Piedade, João F. Pinheiro, P. Relvas, Angelo Rivetti, Pedro Miguel Rodrigues, José C. Silva, Manuel M. Silva, Isabel C. Teixeira, João Paulo Teixeira, Andreia Trindade, João Varela
On-Detector Electronics of the Clear PEM Scanner. BIODEVICES (2009)
Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems. J. Low Power Electron. 4 (3) (2008)
Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. DDECS (2008)
Jorge Semião, João Varela, Judit Freijedo, Juan J. Rodríguez-Andina, Carlos Leong, João Paulo Teixeira, Isabel C. Teixeira
Robust solution for synchronous communication among multi clock domains. APCCAS (2008)
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. IOLTS (2008)
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Time Management for Low-Power Design of Digital Systems. J. Low Power Electron. 4 (3) (2008)
Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. DFT (2007)
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. IOLTS (2007)
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. DDECS (2007)
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. ISVLSI (2007)
Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. IOLTS (2006)
F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. DDECS (2006)
Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
Using Multiple Clock Schemes and Multi-Temperature Test for Dynamic Fault Detection in Digital Systems. LATW (2006)
Carlos Leong, P. Bento, Pedro Miguel Rodrigues, Andreia Trindade, J. C. Silva, Pedro Lousã, Joel Rego, J. Nobre, João Varela, João Paulo Teixeira, Isabel C. Teixeira
Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. FPL (2005)
D. Barros Júnior, Marcial Jesús Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, João Paulo Teixeira
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. J. Electron. Test. 21 (4) (2005)
Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. IOLTS (2005)
Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Modeling and Simulation of Time Domain Faults in Digital Systems. IOLTS (2004)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electron. Test. 20 (4) (2004)
Rui Ribeiro, Octávio Páscoa Dias, João Paulo Teixeira, Isabel C. Teixeira
Hardware/software solution for the automation and real-time control of a wine bottling production line. ETFA (1) (2003)
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. IOLTS (2003)
Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. DATE (2003)
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. DFT (2002)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC (2002)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
On High-Quality, Low Energy BIST Preparation at RT-Level. LATW (2002)
Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. J. Electron. Test. 18 (2) (2002)
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. J. Electron. Test. 18 (3) (2002)
Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
Embedded tutorial: TRP: integrating embedded test and ATE. DATE (2001)
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. ITC (2001)
Hugo Lérias, João Luz, Pedro Moura, Ana Mendes, Isabel C. Teixeira, João Paulo Teixeira
Towards E-Management as Enabler for Accelerated Change. ICEIS (2) (2001)
Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
RTL design validation, DFT and test pattern generation for high defects coverage. ETW (2001)
Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. J. Electron. Test. 17 (3-4) (2001)
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. IOLTW (2001)
Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
RTL-based functional test generation for high defects coverage in digital SOCs. ETW (2000)
Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira, Leandro Buss Becker, Carlos Eduardo Pereira
Optimizing Functional distribution in Complex System Design. DIPES (2000)
Octávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Quality of Electronic Design: From Architectural Level to Test Coverage. ISQED (2000)
Leandro Buss Becker, Carlos Eduardo Pereira, Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira
MOSYS A Methodology for Automatic Object Identification from System Specification. ISORC (2000)
Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira
Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures. J. Electron. Test. 14 (1-2) (1999)
Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. VTS (1999)
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Defect-oriented test quality assessment using fault sampling and simulation. ITC (1998)
Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira, Carlos Eduardo Pereira
An OO Based Methodology for Real-Time HW/SW Systems Modeling. DIPES (1998)
Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. DFT (1997)
Mario Calha, João Paulo Teixeira, Isabel C. Teixeira
HW/SW specification using OOM techniques. RSP (1996)
Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
Integrated Approach for Circuit and Fault Extraction of VLSI Circuits. DFT (1996)
Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira
Test preparation methodology for high coverage of physical defects in CMOS digital ICs. ED&TC (1995)
Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira
Test preparation for high coverage of physical defects in CMOS digital ICs. VTS (1995)
Mario Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. ITC (1994)
P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Realistic Fault Analysis of CMOS Analog Building Blocks. DFT (1993)
A. P. Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. DFT (1993)
M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
Physical DFT for High Coverage of Realistic Faults. ITC (1992)
João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves
A methodology for testability enhancement at layout level. J. Electron. Test. 1 (4) (1991)
João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves, R. Crespo
A strategy for testability enhancement at layout level. EURO-DAC (1990)