Salvador Manich

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 10

Top Topics

Random Number Generator

Countermeasures

Information Security

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

V. Mahboubi, Á. Gómez, Antonio Calomarde, Daniel Arumí, R. Rodríguez, Salvador Manich
On the Fine Tuning of RRAM Resistance Under Variability Using Current Pulses at SET. IOLTS (2024)
Maryam Akbari, Sattar Mirzakuchaki, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Francesca Campabadal, Mireia Bargallo González, Rosa Rodríguez-Montañés
True Random Number Generator Based on the Variability of the High Resistance State of RRAMs. IEEE Access 11 (2023)
Antonio Calomarde, Salvador Manich, Antonio Rubio, Francisco Gámiz
Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact. IEEE Access 10 (2022)
V. Mahboubi, Daniel Arumí, Álvaro Gómez-Pau, R. Rodríguez, Salvador Manich
On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data. DCIS (2022)
Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Juan Bautista Roldán, Mireia Bargallo González, Francesca Campabadal, Liang Fang
Simulation of serial RRAM cell based on a Verilog-A compact model. DCIS (2021)
P. Albiol, Salvador Manich, Daniel Arumí, Rosa Rodríguez-Montañés, A. Gómez-Pau
Low Cost AES Protection Against DPA Using Rolling Codes. DCIS (2021)
Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich
A Calibratable Detector for Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Madalin Neagu, Salvador Manich
Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis. Microelectron. J. 62 (2017)
Daniel Arumí, Salvador Manich, Rosa Rodríguez-Montañés
RRAM based cell for hardware security applications. IVSW (2016)
Madalin-Ioan Neagu, Liviu Miclea, Salvador Manich
Improving security in cache memory by power efficient scrambling technique. IET Comput. Digit. Tech. 9 (6) (2015)
Michael Weiner, Salvador Manich, Georg Sigl
A Low Area Probing Detector for Power Efficient Security ICs. RFIDSec (2014)
Madalin Neagu, Liviu Miclea, Salvador Manich
Interleaved scrambling technique: A novel low-power security layer for cache memories. ETS (2014)
Salvador Manich, Martin Strasser
A Highly Time Sensitive XOR Gate for Probe Attempt Detectors. IEEE Trans. Circuits Syst. II Express Briefs (11) (2013)
Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl
Differential scan-path: A novel solution for secure design-for-testability. ITC (2013)
Salvador Manich, Markus S. Wamser, Georg Sigl
Detection of probing attempts in secure ICs. HOST (2012)
S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich
Design and implementation of Automatic Test Equipment IP module. ETS (2010)
Salvador Manich, L. Garcia-Deiros, Joan Figueras
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electron. Test. 20 (4) (2004)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
BIST Technique by Equally Spaced Test Vector Sequences. VTS (2004)
Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. PATMOS (2003)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW (2003)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC (2002)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
On High-Quality, Low Energy BIST Preparation at RT-Level. LATW (2002)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16 (3) (2000)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) (1999)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, Marcelino B. Santos
Low power BIST by filtering non-detecting vectors. ETW (1999)
Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras
Fault-Secure Parity Prediction Arithmetic Operators. IEEE Des. Test Comput. 14 (2) (1997)
Salvador Manich, Joan Figueras
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. ED&TC (1997)
Salvador Manich, Michael Nicolaidis, Joan Figueras
monitoring. VTS (1996)
Michael Nicolaidis, Salvador Manich, Joan Figueras
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations. ED&TC (1996)