Emili Lupon

Publication Activity (10 Years)

Years Active: 2003-2020
Publications (10 Years): 2

Top Topics

Explicit Expressions

Electronic Circuits

Top Venues

IEEE Trans. Ind. Electron.

IET Circuits Devices Syst.

IEEE Trans. Ind. Informatics

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Álvaro Gómez-Pau, Emili Lupon, Luz Balado, Joan Figueras
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures. IET Circuits Devices Syst. 14 (5) (2020)
Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich
A Calibratable Detector for Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
Sergio Busquets-Monge, Ramkrishan Maheshwari, Joan Nicolas-Apruzzese, Emili Lupon, Stig Munk-Nielsen, Josep Bordonau
Enhanced DC-Link Capacitor Voltage Balancing Control of DC-AC Multilevel Multileg Converters. IEEE Trans. Ind. Electron. 62 (5) (2015)
Emili Lupon, Sergio Busquets-Monge, Joan Nicolas-Apruzzese
FPGA Implementation of a PWM for a Three-Phase DC-AC Multilevel Active-Clamped Converter. IEEE Trans. Ind. Informatics 10 (2) (2014)
Luz Balado, Emili Lupon, Joan Figueras, Miquel Roca, Eugeni Isern, Rodrigo Picos
Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2009)
Luz Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras
Lissajous Based Mixed-Signal Testing for N-Observable Signals. DDECS (2006)
Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA (2004)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
BIST Technique by Equally Spaced Test Vector Sequences. VTS (2004)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW (2003)