Joan Figueras

Publication Activity (10 Years)

Years Active: 1991-2020
Publications (10 Years): 12

Top Venues

ETS

IEEE Trans. Very Large Scale Integr. Syst.

DTIS

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Álvaro Gómez-Pau, Emili Lupon, Luz Balado, Joan Figueras
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures. IET Circuits Devices Syst. 14 (5) (2020)
Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras
Postbond Test of Through-Silicon Vias With Resistive Open Defects. IEEE Trans. Very Large Scale Integr. Syst. 27 (11) (2019)
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing. J. Electron. Test. 33 (3) (2017)
Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras
Mitigating read & write errors in STT-MRAM memories under DVS. ETS (2017)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
Prebond Testing of Weak Defects in TSVs. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
Indirect test of M-S circuits using multiple specification band guarding. Integr. 55 (2016)
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (8) (2016)
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
Analog circuits testing using digitally coded indirect measurements. DTIS (2015)
Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
Power-aware voltage tuning for STT-MRAM reliability. ETS (2015)
Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. DATE (2015)
Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Paolo Prinetto, Joan Figueras
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. DTIS (2015)
Stefano Di Carlo, Marco Indaco, Paolo Prinetto, Elena I. Vatajelu, Rosa Rodríguez-Montañés, Joan Figueras
Reliability estimation at block-level granularity of spin-transfer-torque MRAMs. DFT (2014)
Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras
Post-bond test of Through-Silicon Vias with open defects. ETS (2014)
Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
Sram cell stability metric under transient voltage noise. Microelectron. J. 45 (10) (2014)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
Pre-bond testing of weak defects in TSVs. IOLTS (2014)
Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras
Skew violation verification in digital interconnect signals based on signal addition. IEICE Electron. Express 11 (15) (2014)
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
M-S specification binning based on digitally coded indirect measurements. ETS (2014)
Álvaro Gómez-Pau, Luz Balado, Joan Figueras
M-S test based on specification validation using octrees in the measure space. ETS (2013)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (2) (2013)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
BIST architecture to detect defects in tsvs during pre-bond testing. ETS (2013)
Elena I. Vatajelu, Joan Figueras
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation. DATE (2012)
Elena I. Vatajelu, Joan Figueras
Robustness analysis of 6T SRAMs in memory retention mode under PVT variations. DATE (2011)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (12) (2011)
Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, B. Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, X. Wang, Paul Zuber
New reliability mechanisms in memory design for sub-22nm technologies. IOLTS (2011)
Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Asian Test Symposium (2011)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
Gate Leakage Impact on Full Open Defects in Interconnect Lines. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Elena Ioana Vatajelu, Joan Figueras
Statistical analysis of 6T SRAM data retention voltage under process variation. DDECS (2011)
Madalin Neagu, Liviu Miclea, Joan Figueras
Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies. IOLTS (2011)
Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. ETS (2010)
Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
Diagnosis of full open defects in interconnect lines with fan-out. ETS (2010)
Alvaro Gómez, Ricard Sanahuja, Luz Balado, Joan Figueras
Analog circuit test based on a digital signature. DATE (2010)
Víctor H. Champac, Victor Avendaño, Joan Figueras
Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Luz Balado, Emili Lupon, Joan Figueras, Miquel Roca, Eugeni Isern, Rodrigo Picos
Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2009)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
Delay caused by resistive opens in interconnecting lines. Integr. 42 (3) (2009)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
Experimental Characterization of CMOS Interconnect Open Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (1) (2008)
Francesc Moll, Joan Figueras, Antonio Rubio
Data Dependence of Delay Distribution for a Planar Bus. PATMOS (2008)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
Full Open Defects in Nanometric CMOS. VTS (2008)
Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
Time-dependent Behaviour of Full Open Defects in Interconnect Lines. ITC (2008)
Salvador Manich, L. Garcia-Deiros, Joan Figueras
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
Diagnosis of Full Open Defects in Interconnecting Lines. VTS (2007)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. VTS (2007)
Luz Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras
Lissajous Based Mixed-Signal Testing for N-Observable Signals. DDECS (2006)
R. Sanahuja, Victor Barcons, Luz Balado, Joan Figueras
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning. J. Electron. Test. 21 (3) (2005)
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
Defective behaviours of resistive opens in interconnect lines. ETS (2005)
Victor Avendaño, Víctor H. Champac, Joan Figueras
Signal integrity verification using high speed monitors. ETS (2004)
Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. J. Electron. Test. 20 (2) (2004)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electron. Test. 20 (4) (2004)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
BIST Technique by Equally Spaced Test Vector Sequences. VTS (2004)
Victor Avendaño, Víctor H. Champac, Joan Figueras
Signal integrity loss in bus lines due to open shielding defects. ETW (2003)
Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden
Test Engineering Education in Europe: the EuNICE-Test Project. MSE (2003)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW (2003)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC (2002)
Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. IOLTW (2002)
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
On High-Quality, Low Energy BIST Preparation at RT-Level. LATW (2002)
Antoni Ferré, Joan Figueras
Leakage power bounds in CMOS digital technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (6) (2002)
Paolo Prinetto, Joan Figueras
Guest Editorial. J. Electron. Test. 17 (3-4) (2001)
Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian
IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC (2001)
Antonio Zenteno, Víctor H. Champac, Joan Figueras
Detectability Conditions of Full Opens in the Interconnections. J. Electron. Test. 17 (2) (2001)
Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. 17 (3-4) (2001)
Anotnio Zenteno, Víctor H. Champac, Joan Figueras
Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. LATW (2001)
Joan Figueras
Test Challenges in a Nanometric World. LATW (2001)
Anna Maria Brosa, Joan Figueras
Digital Signature Proposal for Mixed-Signal Circuits. J. Electron. Test. 17 (5) (2001)
Antoni Ferré, Joan Figueras
Estimator. J. Electron. Test. 17 (3-4) (2001)
Antoni Ferré, Joan Figueras
estimator. ETW (2000)
Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium (2000)
Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI (2000)
Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
Analyzing the test generation problem for an application-oriented test of FPGAs. ETW (2000)
Anna Maria Brosa, Joan Figueras
Digital signature proposal for mixed-signal circuits. ITC (2000)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. 16 (3) (2000)
Antonio Zenteno, Víctor H. Champac, Joan Figueras
Detectability Dependency on Test Generation Process for Interconnection Opens. LATW (2000)
Anna Maria Brosa, Joan Figueras
On Maximizing the Coverage of Catastrophic and Parametric Faults. J. Electron. Test. 16 (3) (2000)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16 (3) (2000)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. 16 (5) (2000)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
Test Configuration Generation for FPGA Logic Cells. LATW (2000)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE (1999)
Josep Rius, Joan Figueras
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. DATE (1999)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. 14 (1-2) (1999)
Anna Maria Brosa, Joan Figueras
On maximizing the coverage of catastrophic and parametric faults. ETW (1999)
Anna Maria Brosa, Joan Figueras
Characterization of Floating Gate Defects in Analog Cells. J. Electron. Test. 14 (1-2) (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) (1999)
Víctor H. Champac, José Castillejos, Joan Figueras
IDDQ Testing of Opens in CMOS SRAMs. J. Electron. Test. 15 (1-2) (1999)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, Marcelino B. Santos
Low power BIST by filtering non-detecting vectors. ETW (1999)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium (1999)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW (1999)
Anna Maria Brosa, Joan Figueras
On Optimizing Test Strategies for Analog Cells. Great Lakes Symposium on VLSI (1999)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium (1998)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE (1998)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL (1998)
Rosa Rodríguez-Montañés, Joan Figueras
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. DATE (1998)
Antoni Ferré, Joan Figueras
Characterization of leakage power in CMOS technologies. ICECS (1998)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
SRAM-based FPGA's: testing the LUT/RAM modules. ITC (1998)
Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
Novel Technique for Testing FPGAs. DATE (1998)
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. 15 (1) (1998)
Víctor H. Champac, José Castillejos, Joan Figueras
IDDQ Testing of Opens in CMOS SRAMs. VTS (1998)
Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
IDDQ testing: state of the art and future trends. Integr. 26 (1-2) (1998)
Víctor H. Champac, Joan Figueras
Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. VLSI Design 5 (3) (1997)
Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras
Fault-Secure Parity Prediction Arithmetic Operators. IEEE Des. Test Comput. 14 (2) (1997)
Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
Power Dissipation During Testing: Should We Worry About it? VTS (1997)
Rosa Rodríguez-Montañés, Joan Figueras
Bridges in sequential CMOS circuits: current-voltage signatur. VTS (1997)

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Publication Activity (10 Years)

Top Topics

Top Venues

Joan Figueras