Loïs Guiller

Publication Activity (10 Years)

Years Active: 1999-2006
Publications (10 Years): 0

Publications

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22 (1) (2006)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20 (6) (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DATE (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DELTA (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC (2003)
Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur
Integrating DFT in the Physical Synthesis Flow. ITC (2002)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium (2001)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW (2001)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS (2001)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium (2000)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16 (3) (2000)
Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
Low power BIST design by hypergraph partitioning: methodology and architectures. ITC (2000)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium (1999)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, Marcelino B. Santos
Low power BIST by filtering non-detecting vectors. ETW (1999)