Low power BIST design by hypergraph partitioning: methodology and architectures.
Patrick GirardChristian LandraultLoïs GuillerSerge PravossoudovitchPublished in: ITC (2000)
Keyphrases
- low power
- single chip
- high speed
- power consumption
- low cost
- low power consumption
- vlsi architecture
- logic circuits
- gate array
- cmos technology
- wireless transmission
- ultra low power
- power dissipation
- digital signal processing
- design methodology
- high power
- power reduction
- design process
- mixed signal
- vlsi circuits
- nm technology
- text mining
- image processing