Christian Landrault

Publication Activity (10 Years)

Years Active: 1978-2009
Publications (10 Years): 0

Publications

Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. 25 (2-3) (2009)
Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. 3 (6) (2009)
Christian Landrault
Something I Always Wanted to Know About Test, But Was Afraid to Ask. ETS (2009)
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Using TMR Architectures for Yield Improvement. DFT (2008)
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
SoC Yield Improvement: Redundant Architectures to the Rescue? ITC (2008)
Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. 24 (4) (2008)
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS (2008)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Improving Diagnosis Resolution without Physical Information. DELTA (2008)
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE (2007)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Fast Bridging Fault Diagnosis using Logic Information. ATS (2007)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
DERRIC: A Tool for Unified Logic Diagnosis. ETS (2007)
Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga
A concurrent approach for testing address decoder faults in eFlash memories. ITC (2007)
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS (2007)
Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS (2007)
Christian Landrault, Erik Jan Marinissen
Editorial. IET Comput. Digit. Tech. 1 (3) (2007)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Mixed Approach for Unified Logic Diagnosis. DDECS (2007)
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS (2007)
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS (2007)
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS (2007)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22 (1) (2006)
Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault
Power-Aware Test Data Compression for Embedded IP Cores. ATS (2006)
Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
An Overview of Failure Mechanisms in Embedded Flash Memories. VTS (2006)
Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC (2006)
Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC (2005)
Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS (2005)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20 (6) (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DATE (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DELTA (2004)
Christian Landrault
Guest Editorial. J. Electron. Test. 19 (4) (2003)
Marie-Lise Flottes, Christian Landrault, A. Petitqueux
A Unified DFT Approach for BIST and External Test. J. Electron. Test. 19 (1) (2003)
Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
A Ring Architecture Strategy for BIST Test Pattern Generation. J. Electron. Test. 19 (3) (2003)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC (2003)
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Power Driven Chaining of Flip-Flops in Scan Architectures. ITC (2002)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. 19 (5) (2002)
René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
On Using Efficient Test Sequences for BIST. VTS (2002)
Christian Landrault
Guest Editorial. J. Electron. Test. 18 (2) (2002)
René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. 18 (2) (2002)
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Test Power: a Big Issue in Large SOC Designs. DELTA (2002)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium (2001)
Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. 17 (3-4) (2001)
Luiz Carlos Pessoa Albini, Elias P. Duarte Jr., Leonardo L. Giovanini, Marie-Lise Flottes, Christian Landrault, A. Petitqueux
Generalized Distributed Comparison-Based System-Level Diagnosis. LATW (2001)
David Bernard, Christian Landrault, Pascal Nouet
Interconnect Capacitance Modelling in a VDSM CMOS Technology. VLSI-SOC (2001)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW (2001)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS (2001)
René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
On hardware generation of random single input change test sequences. ETW (2001)
René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC (2001)
Christian Landrault
Guest Editorial. J. Electron. Test. 16 (3) (2000)
Marie-Lise Flottes, Christian Landrault, A. Petitqueux
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Asian Test Symposium (2000)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium (2000)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16 (3) (2000)
Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
Low power BIST design by hypergraph partitioning: methodology and architectures. ITC (2000)
Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Delay fault testing: choosing between random SIC and random MIC test sequences. ETW (2000)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW (2000)
Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault
Hidden Markov and Independence Models with Patterns for Sequential BIST. VTS (2000)
Marie-Lise Flottes, Christian Landrault, A. Petitqueux
Partial set for flip-flops based on state requirement for non-scan BIST scheme. ETW (1999)
Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. 14 (1-2) (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) (1999)
Christian Landrault
Guest Editorial. J. Electron. Test. 14 (1-2) (1999)
Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
On calculating efficient LFSR seeds for built-in self test. ETW (1999)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium (1999)
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, Marcelino B. Santos
Low power BIST by filtering non-detecting vectors. ETW (1999)
A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. DATE (1999)
Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium (1998)
Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium (1998)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
A gate resizing technique for high reduction in power consumption. ISLPED (1997)
Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch
An optimized BIST test pattern generator for delay testing. VTS (1997)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
A non-iterative gate resizing algorithm for high reduction in power consumption. Integr. 24 (1) (1997)
J. Abraham, Phyllis G. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse
Hardware Test: Can We Learn from Software Testing? VTS (1997)
Christophe Fagot, Patrick Girard, Christian Landrault
On Using Machine Learning for Logic BIST. ITC (1997)
Marc Perbost, Ludovic Le Lan, Christian Landrault
Automatic Testability Analysis of Boards and MCMs at Chip Level. Asian Test Symposium (1997)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC (1996)
S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
A new test pattern generation method for delay fault testing. VTS (1996)
P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ED&TC (1996)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
Delay fault diagnosis in sequential circuits based on path tracing. Integr. 19 (3) (1995)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS (1995)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch
An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Test. 6 (3) (1995)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
A trace-based method for delay fault diagnosis in synchronous sequential circuits. ED&TC (1995)
S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault
Test configurations to enhance the testability of sequential circuits. Asian Test Symposium (1995)
Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre
Is High-Level Test Synthesis Just Design for Test? ITC (1995)
D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC (1994)
D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC (1993)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Des. Test Comput. 9 (4) (1992)
Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault
BIST linear generator based on complemented outputs. VTS (1992)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch
A Novel Approach to Delay-Fault Diagnosis. DAC (1992)
Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault
Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors. VLSI Design (1992)
Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
A New Reliable Method for Delay-Fault Diagnosis. VLSI Design (1992)
Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch
Fault modeling and fault equivalence in CMOS technology. J. Electron. Test. 2 (3) (1991)
Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch
Fault modelling and fault equivalence in CMOS technology. EURO-DAC (1990)
Yves Crouzet, Christian Landrault
Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor. IEEE Trans. Computers 29 (6) (1980)
Christian Landrault, Jean-Claude Laprie
SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems. Jerusalem Conference on Information Technology (1978)
Alain Costes, Christian Landrault, Jean-Claude Laprie
Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults. IEEE Trans. Computers 27 (6) (1978)