Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.
Patrick GirardLoïs GuillerChristian LandraultSerge PravossoudovitchPublished in: Asian Test Symposium (1999)
Keyphrases
- low power
- power consumption
- power reduction
- power dissipation
- logic circuits
- cmos technology
- low power consumption
- nm technology
- single chip
- gate array
- high speed
- low cost
- power saving
- vlsi architecture
- power management
- digital signal processing
- mixed signal
- energy efficiency
- vlsi circuits
- clock gating
- data center
- low voltage
- energy saving
- delay insensitive
- ultra low power
- circuit design