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A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Yannick Bonhomme
Patrick Girard
Loïs Guiller
Christian Landrault
Serge Pravossoudovitch
Published in:
Asian Test Symposium (2001)
Keyphrases
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low power
power consumption
high speed
logic circuits
low cost
delay insensitive
power saving
vlsi architecture
high power
cmos technology
vlsi circuits
low power consumption
digital signal processing
embedded systems
single chip
wireless transmission
gate array
real time
image sensor