Yannick Bonhomme

Publication Activity (10 Years)

Years Active: 2001-2013
Publications (10 Years): 0

Top Topics

Minimum Distance

Error Correction

Error Detection

Top Venues

J. Electron. Test.

Publications

Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. DATE (2013)
Valentin Gherman, Samuel Evain, Yannick Bonhomme
Memory Reliability Improvement Based on Maximized Error-Correcting Codes. J. Electron. Test. 29 (4) (2013)
Valentin Gherman, Samuel Evain, Yannick Bonhomme
Memory reliability improvements based on maximized error-correcting codes. ETS (2012)
Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme
Error prediction based on concurrent self-test and reduced slack time. DATE (2011)
Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme
Programmable extended SEC-DED codes for memory errors. VTS (2011)
Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme
Generalized parity-check matrices for SEC-DED codes with fixed parity. IOLTS (2011)
Samuel Evain, Yannick Bonhomme, Valentin Gherman
Programmable restricted SEC codes to mask permanent faults in semiconductor memories. IOLTS (2010)
Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme
System-level hardware-based protection of memories against soft-errors. DATE (2009)
Richard Buchmann, Mickael Cartron, Yannick Bonhomme
Transaction-based modeling for large scale simulations of heterogeneous systems. SimuTools (2009)
Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme
Power-On Controller for high lifetime wireless sensor nodes. WSAN (2008)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22 (1) (2006)
Patrick Girard, Yannick Bonhomme
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. J. Low Power Electron. 1 (1) (2005)
Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard
An efficient scan tree design for test time reduction. ETS (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20 (6) (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DATE (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DELTA (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC (2003)
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Power Driven Chaining of Flip-Flops in Scan Architectures. ITC (2002)
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Test Power: a Big Issue in Large SOC Designs. DELTA (2002)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium (2001)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW (2001)