Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.
Patrick GirardYannick BonhommePublished in: J. Low Power Electron. (2005)
Keyphrases
- low power
- power consumption
- single chip
- low power consumption
- power dissipation
- high power
- high speed
- low cost
- power reduction
- logic circuits
- vlsi architecture
- digital signal processing
- gate array
- ultra low power
- power management
- mixed signal
- cmos technology
- energy efficiency
- energy dissipation
- vlsi circuits
- nm technology