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A Gated Clock Scheme for Low Power Testing of Logic Cores.
Yannick Bonhomme
Patrick Girard
Loïs Guiller
Christian Landrault
Serge Pravossoudovitch
Arnaud Virazel
Published in:
J. Electron. Test. (2006)
Keyphrases
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low power
power consumption
high speed
logic circuits
low cost
delay insensitive
high power
single chip
vlsi circuits
vlsi architecture
power dissipation
real time
power saving
wireless transmission
low power consumption
mixed signal
digital signal processing
cmos technology
image sensor
signal processor
gate array