An adjacency-based test pattern generator for low power BIST design.
Patrick GirardLoïs GuillerChristian LandraultSerge PravossoudovitchPublished in: Asian Test Symposium (2000)
Keyphrases
- low power
- pattern generator
- power consumption
- single chip
- low cost
- low power consumption
- vlsi architecture
- high speed
- built in self test
- logic circuits
- cmos technology
- digital signal processing
- gate array
- wireless transmission
- power dissipation
- ultra low power
- high power
- nm technology
- image segmentation
- mixed signal
- image sensor
- data flow
- embedded systems
- real time