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A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.
Patrick Girard
Loïs Guiller
Christian Landrault
Serge Pravossoudovitch
Hans-Joachim Wunderlich
Published in:
VTS (2001)
Keyphrases
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low power
pattern generator
power consumption
high speed
low cost
high power
single chip
digital signal processing
power saving
low power consumption
vlsi circuits
vlsi architecture
power reduction
gate array
logic circuits
nm technology
image sensor
wireless sensor networks