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A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.

Patrick GirardChristian LandraultV. MoredaSerge PravossoudovitchArnaud Virazel
Published in: J. Electron. Test. (1999)
Keyphrases
  • built in self test
  • integrated circuit
  • real time
  • neural network
  • graphical models
  • statistical significance