Marie-Lise Flottes

ORCID

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 41

Top Venues

Publications

Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
Utilizing layout effects for analog logic locking. J. Cryptogr. Eng. 14 (2) (2024)
Sophie Dupuis, Nassim Riadi, Clémy Moroukian, Florence Azaïs, Marie-Lise Flottes
Logic Locking: Exploration of a new key-gate based on tristate logic. LATS (2024)
Nassim Riadi, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes
Power Analysis Attack Against post-SAT Logic Locking schemes. ETS (2024)
Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
Utilizing Layout Effects for Analog Logic Locking. CoRR (2024)
Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE (2024)
F. Almeida, Levent Aksoy, Q.-L. Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini
Resynthesis-based Attacks Against Logic Locking. CoRR (2023)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. 31 (6) (2023)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
Hybrid Protection of Digital FIR Filters. CoRR (2023)
L. Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS (2023)
Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini
Resynthesis-based Attacks Against Logic Locking. ISQED (2023)
S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. ETS (2022)
Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
Leveraging Layout-based Effects for Locking Analog ICs. CoRR (2022)
Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
Leveraging Layout-based Effects for Locking Analog ICs. ASHES@CCS (2022)
S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. ETS (2021)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
High-level Intellectual Property Obfuscation via Decoy Constants. CoRR (2021)
Quang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
On Preventing SAT Attack with Decoy Key-Inputs. ISVLSI (2021)
L. Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel
Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS (2021)
Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS (2021)
Quang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
A Secure Scan Controller for Protecting Logic Locking. IOLTS (2020)
Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS (2020)
Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Encryption-Based Secure JTAG. DDECS (2019)
Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Stream vs block ciphers for scan encryption. Microelectron. J. 86 (2019)
Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
SECCS: SECure Context Saving for IoT Devices. CoRR (2019)
Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (3) (2019)
Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW (2019)
Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre
Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. DTIS (2019)
Sophie Dupuis, Marie-Lise Flottes
Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. J. Electron. Test. 35 (3) (2019)
Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A Survey on Security Threats and Countermeasures in IEEE Test Standards. IEEE Des. Test 36 (3) (2019)
Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
A New Secure Stream Cipher for Scan Chain Encryption. IVSW (2018)
Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC (2018)
Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS (2018)
Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
Encryption of test data: which cipher is better? PRIME (2018)
Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Marie-Lise Flottes, Olivier Potin, Giorgio Di Natale, Bruno Rouzeyre, Rodrigo Possamai Bastos
Assessing body built-in current sensors for detection of multiple transient faults. Microelectron. Reliab. (2018)
Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
SI ECCS: SECure context saving for IoT devices. DTIS (2018)
Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Des. Test 35 (2) (2018)
Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Experimentations on scan chain encryption with PRESENT. IVSW (2017)
Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
Hacking the Control Flow error detection mechanism. IVSW (2017)
Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo
Scan chain encryption for the test, diagnosis and debug of secure circuits. ETS (2017)
Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. ISVLSI (2016)
Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Using outliers to detect stealthy hardware trojan triggering? IVSW (2016)
Stephan De Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes
Frontside Versus Backside Laser Injection: A Comparative Study. ACM J. Emerg. Technol. Comput. Syst. 13 (1) (2016)
Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel
3D DFT Challenges and Solutions. ISVLSI (2015)
Marie-Lise Flottes, Sophie Dupuis, Papa-Sidi Ba, Bruno Rouzeyre
On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS (2015)
Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Max Dutertre
Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits. ISVLSI (2015)
Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre
Session-less based thermal-aware 3D-SIC test scheduling. ETS (2015)
Papa-Sidi Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
Hardware Trojan prevention using layout-level design approach. ECCTD (2015)
Sophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
New testing procedure for finding insertion sites of stealthy hardware trojans. DATE (2015)
Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. IOLTS (2014)
Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Customized cell detector for laser-induced-fault detection. IOLTS (2014)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche
Built-in self-test for manufacturing TSV defects before bonding. VTS (2014)
Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier
Laser-induced fault effects in security-dedicated circuits. VLSI-SoC (2014)
Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noemie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di Natale
Laser attacks on integrated circuits: From CMOS to FD-SOI. DTIS (2014)
Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Guillaume Hubert
Layout-aware laser fault injection simulation and modeling: From physical level to gate level. DTIS (2014)
Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Alexandre Sarafianos
Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectron. Reliab. 54 (9-10) (2014)
Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel
2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI (2014)
Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hély, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert
Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) (2014)
Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Test Versus Security: Past and Present. IEEE Trans. Emerg. Top. Comput. 2 (1) (2014)
Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. J. Electron. Test. 29 (3) (2013)
Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Laser-Induced Fault Simulation. DSD (2013)
Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
A bulk built-in sensor for detection of fault attacks. HOST (2013)
Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale
Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectron. Reliab. 53 (9-11) (2013)
Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS (2013)
Hakim Zimouche, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A BIST method for TSVs pre-bond test. IDT (2013)
Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A novel differential scan attack on advanced DFT structures. ACM Trans. Design Autom. Electr. Syst. 18 (4) (2013)
Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Inf. Secur. J. A Glob. Perspect. 22 (5-6) (2013)
Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Secure JTAG Implementation Using Schnorr Protocol. J. Electron. Test. 29 (2) (2013)
Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A smart test controller for scan chains in secure circuits. IOLTS (2013)
Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Multilevel Ionizing-Induced Transient Fault Simulator. Inf. Secur. J. A Glob. Perspect. 22 (5-6) (2013)
Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale
A 3D IC BIST for pre-bond test of TSVs using ring oscillators. NEWCAS (2013)
Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
On-chip test comparison for protecting confidential data in secure ICs. ETS (2012)
Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
A New Scan Attack on RSA in Presence of Industrial Countermeasures. COSADE (2012)
Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures. DFT (2012)
Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. Microelectron. Reliab. 52 (9-10) (2012)
Jean DaRolt, Amitabh Das, Santosh Ghosh, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Scan attacks on side-channel and fault attack resistant public-key implementations. J. Cryptogr. Eng. 2 (4) (2012)
Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Are advanced DfT structures sufficient for preventing scan-attacks? VTS (2012)
Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
New security threats against chips containing scan chain structures. HOST (2011)
Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. DFT (2011)
Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS (2011)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal
Power consumption traces realignment to improve differential power analysis. DDECS (2011)
Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Timing issues for an efficient use of concurrent error detection codes. LATW (2011)
Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Evaluation of concurrent error detection techniques on the advanced encryption standard. IOLTS (2010)
Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. ETS (2010)
Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
Self-Test Techniques for Crypto-Devices. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA (2010)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Ensuring high testability without degrading security: Embedded tutorial on "test and security". DDECS (2010)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
Execution time reduction of Differential Power Analysis experiments. LATW (2009)
Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. J. Electron. Test. 25 (4-5) (2009)
Beatrice Pradarelli, Laurent Latorre, Marie-Lise Flottes, Yves Bertrand, Pascal Nouet
Remote Labs for Industrial IC Testing. IEEE Trans. Learn. Technol. 2 (4) (2009)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
An Integrated Validation Environment for Differential Power Analysis. DELTA (2008)
Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard
Wireless Test Structure for Integrated Systems. ITC (2008)
Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre
Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI (2008)
M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA (2008)
Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
A Reliable Architecture for the Advanced Encryption Standard. ETS (2008)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS (2007)
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS (2007)
Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
Test data compression and TAM design. VLSI-SoC (2007)
Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
Compression-based SoC Test Infrastructures. VLSI-SoC (Selected Papers) (2007)
David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
Securing Scan Control in Crypto Chips. J. Electron. Test. 23 (5) (2007)
Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
Mutation Sampling Technique for the Generation of Structural Test Data CoRR (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Marie-Lise Flottes