Josep Rius

Publication Activity (10 Years)

Years Active: 1992-2015
Publications (10 Years): 0

Top Topics

Power Distribution Networks

Dynamic Power Management

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Josep Rius
Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Josep Rius
IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Josep Rius
A method for detecting resistive opens in buses. IOLTS (2010)
Josep Rius
Two-dimensional communication of networked devices through a single conductive surface. INSS (2010)
Josep Rius
A single conductive surface as communication media for networked devices. BODYNETS (2010)
Pablo Maqueda, Josep Rius
Analysis of the extra delay on interconnects caused by resistive opens and shorts. IOLTS (2009)
Josep Rius, Maurice Meijer
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors. IEEE J. Solid State Circuits 44 (2) (2009)
Josep Rius, Luis Elvira Villagra, Maurice Meijer
A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits. ETS (2009)
Josep Rius, Maurice Meijer, José Pineda de Gyvez
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. J. Low Power Electron. 2 (1) (2006)
Josep Rius, José Pineda de Gyvez, Maurice Meijer
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. PATMOS (2005)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
BIST Technique by Equally Spaced Test Vector Sequences. VTS (2004)
Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. PATMOS (2003)
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW (2003)
Bram Kruseman, Stefan van den Oetelaar, Josep Rius
Comparison of IDDQ Testing and Very-Low Voltage Testing. ITC (2002)
Josep Rius, Joan Figueras
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. DATE (1999)
Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
IDDQ testing: state of the art and future trends. Integr. 26 (1-2) (1998)
Josep Rius, Joan Figueras
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. J. Electron. Test. 9 (3) (1996)
Josep Rius, Joan Figueras
defective CMOS circuits by depowering. VTS (1995)
Josep Rius, Joan Figueras
Proportional BIC sensor for current testing. J. Electron. Test. 3 (4) (1992)