Georg Sigl

ORCID

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 125

Top Venues

IACR Cryptol. ePrint Arch.

CoRR

DATE

HOST

Technical University Munich, Germany (PHD)

Education History

Technical University Munich, Germany

PHD

Publications

Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann
ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates. DATE (2024)
Patrick Karl, Jonas Schupp, Tim Fritzmann, Georg Sigl
Post-Quantum Signatures on RISC-V with Hardware Acceleration. ACM Trans. Embed. Comput. Syst. 23 (2) (2024)
Michael Mildner, Michaela Brunner, Michael Gruber, Johanna Baehr, Georg Sigl
Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering. DDECS (2024)
Matthias Probst, Manuel Brosch, Michael Gruber, Georg Sigl
DOMREP II. HOST (2024)
Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 32 (2) (2024)
Felix Oberhansl, Tim Fritzmann, Thomas Pöppelmann, Debapriya Basu Roy, Georg Sigl
Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography. J. Cryptogr. Eng. 14 (1) (2024)
Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE (2024)
Patrick Karl, Jonas Schupp, Georg Sigl
The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+. COSADE (2024)
Michaela Brunner, Hye-Hyun Lee, Alexander Hepp, Johanna Baehr, Georg Sigl
Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. DDECS (2024)
Matthias Probst, Manuel Brosch, Georg Sigl
Side-Channel Analysis of Integrate-and-Fire Neurons within Spiking Neural Networks. IACR Cryptol. ePrint Arch. 2023 (2023)
Michaela Brunner, Hye-Hyun Lee, Alexander Hepp, Johanna Baehr, Georg Sigl
Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. CoRR (2023)
Patrick Karl, Jonas Schupp, Georg Sigl
The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+. IACR Cryptol. ePrint Arch. 2023 (2023)
Mathieu Gross, Robert Kunzelmann, Georg Sigl
CPU to FPGA Power Covert Channel in FPGA-SoCs. IACR Cryptol. ePrint Arch. 2023 (2023)
Mathieu Gross, Jonas Krautter, Dennis Gnad, Michael Gruber, Georg Sigl, Mehdi B. Tahoori
FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU. ASP-DAC (2023)
Matthias Ludwig, Ann-Christin Bette, Bernhard Lippmann, Georg Sigl
Counterfeit Detection by Semiconductor Process Technology Inspection. ETS (2023)
Seyed Hamidreza Moghadas, Michael Pehl, Georg Sigl
ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Michaela Brunner, Alexander Hepp, Johanna Baehr, Georg Sigl
Toward a Human-Readable State Machine Extraction. ACM Trans. Design Autom. Electr. Syst. 27 (6) (2022)
Manuel Brosch, Matthias Probst, Georg Sigl
Counteract Side-Channel Analysis of Neural Networks by Shuffling. DATE (2022)
Patrick Karl, Tim Fritzmann, Georg Sigl
Hardware Accelerated FrodoKEM on RISC-V. DDECS (2022)
Maximilian Egger, Thomas Schamberger, Lars Tebelmann, Florian Lippert, Georg Sigl
A Second Look at the ASCAD Databases. COSADE (2022)
Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl
Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC. J. Cryptogr. Eng. 12 (2) (2022)
Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. ICCAD (2022)
Thomas Schamberger, Lukas Holzbaur, Julian Renner, Antonia Wachter-Zeh, Georg Sigl
A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. IACR Cryptol. ePrint Arch. 2022 (2022)
Tim Fritzmann, Michiel Van Beirendonck, Debapriya Basu Roy, Patrick Karl, Thomas Schamberger, Ingrid Verbauwhede, Georg Sigl
Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022 (1) (2022)
Patrick Karl, Jonas Schupp, Tim Fritzmann, Georg Sigl
Post-Quantum Signatures on RISC-V with Hardware Acceleration. IACR Cryptol. ePrint Arch. 2022 (2022)
Bodo Selmke, Maximilian Pollanka, Andreas Duensing, Emanuele Strieder, Hayden Wen, Michael Mittermair, Reinhard Kienberger, Georg Sigl
On the application of Two-Photon Absorption for Laser Fault Injection attacks Pushing the physical boundaries for Laser-based Fault Injection. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022 (4) (2022)
Mathieu Gross, Konrad Hohentanner, Stefan Wiehler, Georg Sigl
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM. ACM Trans. Reconfigurable Technol. Syst. 15 (1) (2022)
Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. CoRR (2022)
Alexander Hepp, Johanna Baehr, Georg Sigl
Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. DATE (2022)
Michael Gruber, Georg Sigl
TOFU - Toggle Count Analysis made simple. IACR Cryptol. ePrint Arch. 2022 (2022)
Johanna Baehr, Alexander Hepp, Michaela Brunner, Maja Malenko, Georg Sigl
Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. DSD (2022)
Thomas Schamberger, Lukas Holzbaur, Julian Renner, Antonia Wachter-Zeh, Georg Sigl
A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. PQCrypto (2022)
Stefan Hristozov, Manuel Huber, Lei Xu, Jaro Fietz, Marco Liess, Georg Sigl
The Cost of OSCORE and EDHOC for Constrained Devices. CoRR (2021)
Alexander Hepp, Georg Sigl
Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. CF (2021)
Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl
Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks. ACM Trans. Embed. Comput. Syst. 20 (2) (2021)
Alexander Kulow, Thomas Schamberger, Lars Tebelmann, Georg Sigl
Finding the Needle in the Haystack: Metrics for Best Trace Selection in Unsupervised Side-Channel Attacks on Blinded RSA. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Tim Fritzmann, Michiel Van Beirendonck, Debapriya Basu Roy, Patrick Karl, Thomas Schamberger, Ingrid Verbauwhede, Georg Sigl
Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2021 (2021)
Stefan Hristozov, Manuel Huber, Lei Xu, Jaro Fietz, Marco Liess, Georg Sigl
The Cost of OSCORE and EDHOC for Constrained Devices. CODASPY (2021)
Michael Gruber, Matthias Probst, Patrick Karl, Thomas Schamberger, Lars Tebelmann, Michael Tempelmeier, Georg Sigl
DOMREP-An Orthogonal Countermeasure for Arbitrary Order Side-Channel and Fault Attack Protection. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Michael Gruber, Patrick Karl, Georg Sigl
Algebraic Fault Analysis of Subterranean 2.0. FDTC (2021)
Thomas Schamberger, Julian Renner, Georg Sigl, Antonia Wachter-Zeh
A Power Side-Channel Attack on the CCA2-Secure HQC KEM. CARDIS (2020)
Martin Striegel, Johann Heyszl, Florian Jakobsmeier, Yacov Matveev, Georg Sigl
Secure and user-friendly over-the-air firmware distribution in a portable faraday cage. WISEC (2020)
Tim Fritzmann, Georg Sigl, Johanna Sepúlveda
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020 (4) (2020)
Debapriya Basu Roy, Tim Fritzmann, Georg Sigl
Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers. ICCAD (2020)
Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann
Machine learning and structural characteristics for reverse engineering. Integr. 72 (2020)
Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR (2020)
Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann
Timing Resilience for Efficient and Secure Circuits. ASP-DAC (2020)
Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Tim Fritzmann, Georg Sigl, Johanna Sepúlveda
Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC. DATE (2020)
Stefan Hristozov, Manuel Huber, Georg Sigl
Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks. HOST (2020)
Matthias Hiller, Ludwig Kürzinger, Georg Sigl
Review of error correction for PUFs and evaluation on state-of-the-art FPGAs. J. Cryptogr. Eng. 10 (3) (2020)
Tim Fritzmann, Georg Sigl, Johanna Sepúlveda
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2020 (2020)
Michaela Brunner, Michael Gruber, Michael Tempelmeier, Georg Sigl
Logic Locking Induced Fault Attacks. ISVLSI (2020)
Thomas Schamberger, Julian Renner, Georg Sigl, Antonia Wachter-Zeh
A Power Side-Channel Attack on the CCA2-Secure HQC KEM. IACR Cryptol. ePrint Arch. 2020 (2020)
Martin Striegel, Florian Jakobsmeier, Yacov Matveev, Johann Heyszl, Georg Sigl
Secure and User-Friendly Over-the-Air Firmware Distribution in a Portable Faraday Cage. CoRR (2020)
Matthias Niedermaier, Dominik Merli, Georg Sigl
A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices. CoRR (2019)
Matthias Niedermaier, Florian Fischer, Dominik Merli, Georg Sigl
Network Scanning and Mapping for IIoT Edge Node Device Security. CoRR (2019)
Vincent Immler, Johannes Obermaier, Kuan Kuan Ng, Fei Xiang Ke, JinYu Lee, Yak Peng Lim, Wei Koon Oh, Keng Hoong Wee, Georg Sigl
Secure Physical Enclosures from Covers with Tamper-Resistance. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019 (1) (2019)
Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann
Machine learning and structural characteristics for reverse engineering. ASP-DAC (2019)
Martin Striegel, Carsten Rolfes, Johann Heyszl, Fabian Helfert, Maximilian Hornung, Georg Sigl
EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. EWSN (2019)
Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl
Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC. ASHES@CCS (2019)
Michaela Brunner, Johanna Baehr, Georg Sigl
Improving on State Register Identification in Sequential Hardware Reverse Engineering. HOST (2019)
Martin Striegel, Carsten Rolfes, Johann Heyszl, Fabian Helfert, Maximilian Hornung, Georg Sigl
EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. CoRR (2019)
Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich
A Calibratable Detector for Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
Matthias Niedermaier, Dominik Merli, Georg Sigl
A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices. MECO (2019)
Stefan Hristozov, Manuel Huber, Georg Sigl
Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks. CoRR (2019)
Matthias Niedermaier, Martin Striegel, Felix Sauer, Dominik Merli, Georg Sigl
Efficient Intrusion Detection on Low-Performance Industrial IoT Edge Node Devices. CoRR (2019)
Michael Tempelmeier, Maximilian Werner, Georg Sigl
Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists. HOST (2019)
Samuel Weiser, Andreas Zankl, Raphael Spreitzer, Katja Miller, Stefan Mangard, Georg Sigl
DATA - Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries. USENIX Security Symposium (2018)
Michael Tempelmeier, Georg Sigl, Jens-Peter Kaps
Experimental Power and Performance Evaluation of CAESAR Hardware Finalists. ReConFig (2018)
Michael Tempelmeier, Fabrizio De Santis, Georg Sigl, Jens-Peter Kaps
The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates. HOST (2018)
Robert Specht, Vincent Immler, Florian Unterstein, Johann Heyszl, Georg Sigl
Dividing the threshold: Multi-probe localized EM analysis on threshold implementations. HOST (2018)
Philipp Koppermann, Eduard Pop, Johann Heyszl, Georg Sigl
18 Seconds to Key Exchange: Limitations of Supersingular Isogeny Diffie-Hellman on Embedded Devices. IACR Cryptol. ePrint Arch. 2018 (2018)
Johannes Obermaier, Vincent Immler, Matthias Hiller, Georg Sigl
A measurement system for capacitive PUF-based security enclosures. DAC (2018)
Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018 (1) (2018)
Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Samuel Weiser, Andreas Zankl, Raphael Spreitzer, Katja Miller, Stefan Mangard, Georg Sigl
DATA - Differential Address Trace Analysis. Krypto-Tag (2018)
Bodo Selmke, Kilian Zinnecker, Philipp Koppermann, Katja Miller, Johann Heyszl, Georg Sigl
Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors. FDTC (2018)
Florian Unterstein, Johann Heyszl, Fabrizio De Santis, Robert Specht, Georg Sigl
High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And An Improved Construction. IACR Cryptol. ePrint Arch. 2018 (2018)
Johanna Sepúlveda, Damian Aboul-Hassan, Georg Sigl, Bernd Becker, Matthias Sauer
Towards the formal verification of security properties of a Network-on-Chip router. ETS (2018)
Georg Sigl, Mathieu Gross, Michael Pehl
Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. ESSCIRC (2018)
Vincent Immler, Johannes Obermaier, Martin Konig, Matthias Hiller, Georg Sigl
B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection. HOST (2018)
Johannes Obermaier, Florian Hauschild, Matthias Hiller, Georg Sigl
An embedded key management system for PUF-based security enclosures. MECO (2018)
Florian Unterstein, Johann Heyszl, Fabrizio De Santis, Robert Specht, Georg Sigl
High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And an Improved Construction. CT-RSA (2018)
Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs. HOST (2017)
Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl
Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication. ReCoSoC (2017)
Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl
Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips. ISVLSI (2017)
Nisha Jacob, Jakob Wittmann, Johann Heyszl, Robert Hesselbarth, Florian Wilde, Michael Pehl, Georg Sigl, Kai Fischer
Securing FPGA SoC configurations independent of their manufacturers. SoCC (2017)
Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Johanna Sepúlveda
Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. Microprocess. Microsystems 52 (2017)
Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Cryptol. ePrint Arch. 2017 (2017)
Robert Hesselbarth, Johann Heyszl, Georg Sigl
Fast and reliable PUF response evaluation from unsettled bistable rings. Microprocess. Microsystems 52 (2017)
Vincent Immler, Matthias Hiller, Johannes Obermaier, Georg Sigl
Take a moment and have some t: Hypothesis testing on raw PUF data. HOST (2017)
Fabrizio De Santis, Andreas Schauer, Georg Sigl
ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications. DATE (2017)
Martha Johanna Sepúlveda, Daniel Flórez, Vincent Immler, Guy Gogniat, Georg Sigl
Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs. Microprocess. Microsystems 50 (2017)
Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl
Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier. Microprocess. Microsystems 52 (2017)
Markus Stefan Wamser, Georg Sigl
Pushing the Limits Further: Sub-Atomic AES. VLSI-SoC (Selected Papers) (2017)
Nisha Jacob, Johann Heyszl, Andreas Zankl, Carsten Rolfes, Georg Sigl
How to Break Secure Boot on FPGA SoCs through Malicious Hardware. IACR Cryptol. ePrint Arch. 2017 (2017)
Markus Stefan Wamser, Georg Sigl
Pushing the limits further: Sub-atomic AES. VLSI-SoC (2017)
Johanna Sepúlveda, Ramon Fernandes, César A. M. Marcon, Daniel Florez, Georg Sigl
A security-aware routing implementation for dynamic data protection in zone-based MPSoC. SBCCI (2017)
Nisha Jacob, Johann Heyszl, Andreas Zankl, Carsten Rolfes, Georg Sigl
How to Break Secure Boot on FPGA SoCs Through Malicious Hardware. CHES (2017)

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Publication Activity (10 Years)

Top Topics

Top Venues

Georg Sigl