CPU to FPGA Power Covert Channel in FPGA-SoCs.

Mathieu Gross Robert Kunzelmann Georg Sigl

Published in: IACR Cryptol. ePrint Arch. (2023)

Keyphrases

high speed
field programmable gate array
real time image processing
hardware implementation
power reduction
real time
low cost
covert channel
signal processing
hardware design
databases
hardware architecture
case study
power consumption
fpga device
information systems
level parallelism