Interleaved scrambling technique: A novel low-power security layer for cache memories.
Madalin NeaguLiviu MicleaSalvador ManichPublished in: ETS (2014)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- image scrambling
- single chip
- high power
- wireless transmission
- information security
- vlsi circuits
- security policies
- vlsi architecture
- low power consumption
- digital signal processing
- security issues
- security mechanisms
- image sensor
- associative memory
- logic circuits
- application layer
- access control
- image processing
- delay insensitive
- power reduction
- image encryption
- cmos technology
- security requirements