José T. de Sousa

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 16

Top Topics

Heterogeneous Computing

Fpga Implementation

Convolutional Neural Networks

Top Venues

Publications

José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias
PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH (2024)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. 16 (1) (2023)
David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 15 (2022)
João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa
IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms 14 (8) (2021)
Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
Configurable Hardware Core for IoT Object Detection. Future Internet 13 (11) (2021)
Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access 9 (2021)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access 8 (2020)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems 77 (2020)
Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa
Implementing CNNs Using a Linear Array of Full Mesh CGRAs. ARC (2020)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Moving Deep Learning to the Edge. Algorithms 13 (5) (2020)
Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa
Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS (2019)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL (2019)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL (2018)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Parallel dot-products for deep learning on FPGA. FPL (2017)
João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
K-means clustering on CGRA. FPL (2017)
João D. Lopes, José T. de Sousa
Versat, a Minimal Coarse-Grain Reconfigurable Array. VECPAR (2016)
Marco Silva Pereira, João Caldinhas Vaz, Carlos Azeredo Leme, José T. de Sousa, João Costa Freire
An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications. ISCAS (2015)
Romanelli Lodron Zuim, José T. de Sousa, Claudionor Coelho
Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction. IET Comput. Digit. Tech. 2 (1) (2008)
Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
A fast SAT solver algorithm best suited to reconfigurable hardware. SBCCI (2006)
Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
A Fast SAT Solver Strategy Based on Negated Clauses. VLSI-SoC (2006)
Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva
Heuristic-Based Backtracking Relaxation for Propositional Satisfiability. J. Autom. Reason. 35 (1-3) (2005)
Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves
A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. FPL (2005)
C. J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. FPL (2004)
Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53 (11) (2004)
Ateet Bhalla, Inês Lynce, José T. de Sousa, João P. Marques Silva
Heuristic Backtracking Algorithms for SAT. MTV (2003)
Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa
Fault Simulation Using Partially Reconfigurable Hardware. FPL (2003)
Ateet Bhalla, Inês Lynce, José T. de Sousa, João P. Marques Silva
Heuristic-Based Backtracking for Propositional Satisfiability. EPIA (2003)
N. A. Reis, José T. de Sousa
On Implementing a Configware/Software SAT Solver. FCCM (2002)
José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura
DARP - A Digital Audio Reconfigurable Processor. FPL (2002)
José T. de Sousa, João P. Marques Silva, Miron Abramovici
A Configurable Hardware/Software Approach to SAT Solving. FCCM (2001)
José T. de Sousa, Vishwani D. Agrawal
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. DATE (2000)
Miron Abramovici, José T. de Sousa
A SAT Solver Using Reconfigurable Hardware and Virtual Logic. J. Autom. Reason. 24 (1/2) (2000)
Miron Abramovici, José T. de Sousa
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. FCCM (1999)
Miron Abramovici, José T. de Sousa, Daniel G. Saab
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. DAC (1999)
José T. de Sousa
On Defect-Level Estimation and the Clustering Effect. VLSI (1999)
José T. de Sousa, Peter Y. K. Cheung
Improved diagnosis of realistic interconnect shorts. ED&TC (1997)
José T. de Sousa, Peter Y. K. Cheung
Diagnosis of Boards for Realistic Interconnect Shorts. J. Electron. Test. 11 (2) (1997)
José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (10) (1996)
José T. de Sousa, T. Shen, Peter Y. K. Cheung
Realistic Fault Extraction for Boards. ED&TC (1996)
José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC (1994)
M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
Physical DFT for High Coverage of Realistic Faults. ITC (1992)
José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira
IC Defects-Based Testability Analysis. ITC (1991)