Mário P. Véstias

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 36

Top Topics

Convolutional Neural Networks

Top Venues

Microprocess. Microsystems

Publications

Manuel Augusto M. Vieira, Gonçalo Galvão, Manuela Vieira, Paula Louro, Mário P. Véstias, Pedro Vieira
Enhancing Urban Intersection Efficiency: Visible Light Communication and Learning-Based Control for Traffic Signal Optimization and Vehicle Management. Symmetry 16 (2) (2024)
Miguel Reis, Mário P. Véstias, Horácio C. Neto
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. ACM Trans. Reconfigurable Technol. Syst. 17 (1) (2024)
José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias
PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH (2024)
Henrique B. Brum, Mário P. Véstias, Horácio C. Neto
LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. ARC (2024)
Maria Inês Frutuoso, Horácio C. Neto, Mário P. Véstias, Rui Policarpo Duarte
Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. Algorithms 16 (3) (2023)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. 16 (1) (2023)
Pedro F. Durães, Mário P. Véstias
Smart Embedded System for Skin Cancer Classification. Future Internet 15 (2) (2023)
David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 15 (2022)
Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. 14 (5) (2022)
João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa
IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms 14 (8) (2021)
Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
Configurable Hardware Core for IoT Object Detection. Future Internet 13 (11) (2021)
Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access 9 (2021)
Mário P. Véstias, Horácio C. Neto
Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. Algorithms 14 (7) (2021)
Mário P. Véstias
Efficient Design of Pruned Convolutional Neural Networks on FPGA. J. Signal Process. Syst. 93 (5) (2021)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access 8 (2020)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems 77 (2020)
Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa
Implementing CNNs Using a Linear Array of Full Mesh CGRAs. ARC (2020)
José M. P. Nascimento, Mário P. Véstias, Gabriel Martín
Hyperspectral Compressive Sensing With a System-On-Chip FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 13 (2020)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Moving Deep Learning to the Edge. Algorithms 13 (5) (2020)
Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa
Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS (2019)
Mário P. Véstias
A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing. Algorithms 12 (8) (2019)
Tiago Peres, Ana Gonçalves, Mário P. Véstias
Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning. ARC (2019)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL (2019)
Ana Gonçalves, Tiago Peres, Mário P. Véstias
Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs. ARC (2019)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL (2018)
Mário P. Véstias, Horácio C. Neto
Improving the area of fast parallel decimal multipliers. Microprocess. Microsystems 61 (2018)
Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Parallel dot-products for deep learning on FPGA. FPL (2017)
Horácio C. Neto, Mário P. Véstias
Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsystems 55 (2017)
João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
K-means clustering on CGRA. FPL (2017)
Jose Canilho, Mário P. Véstias, Horácio C. Neto
Multi-core for K-means clustering on FPGA. FPL (2016)
Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias
XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. ICRC (2016)
José M. P. Nascimento, Mário P. Véstias, Gabriel Martín
FPGA-based architecture for hyperspectral unmixing. IGARSS (2015)
Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto
Enhancing stochastic computations via process variation. FPL (2015)
João Pinhão, Wilson José, Horácio C. Neto, Mário P. Véstias
Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. DSD (2015)
Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto
Designing Hardware/Software Systems for Embedded High-Performance Computing. CoRR (2015)
Tiago Rodrigues, Mário P. Véstias
Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA. DSD (2015)
Mário P. Véstias, Horácio C. Neto
Trends of CPU, GPU and FPGA for high-performance computing. FPL (2014)
Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias
Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. FPL (2014)
Mário P. Véstias, Horácio C. Neto
A Many-Core Overlay for High-Performance Embedded Computing on FPGAs. CoRR (2014)
Mário P. Véstias, Horácio C. Neto, Helena Sarmento
Design of a multiband full-rate ultra-wideband receiver in FPGA. LASCAS (2013)
Horácio C. Neto, Mário P. Véstias
Very low resource table-based FPGA evaluation of elementary functions. ReConFig (2013)
Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto
Design of a massively parallel computing architecture for dense matrix multiplication. LASCAS (2013)
Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias
Analysis of matrix multiplication on high density Virtex-7 FPGA. FPL (2013)
Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
A reconfigurable computing architecture using magnetic tunneling junction memories. FPL (2013)
Mário P. Véstias, Helena Sarmento
Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems. ICCE-Berlin (2012)
Mário P. Véstias, Helena Sarmento
Design of an IEEE 802.15.3c baseband processor in FPGA. ICCE-Berlin (2012)
Mário P. Véstias
Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA. ICCE-Berlin (2012)
Mário P. Véstias, Horácio C. Neto, Helena Sarmento
Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. DSD (2012)
Victor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes
Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions. ICECS (2012)
Mário P. Véstias, Horácio C. Neto, Helena Sarmento
Sliding block Viterbi decoders in FPGA. FPL (2012)
Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. ReConFig (2012)
Mário P. Véstias, Horácio C. Neto
Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. DSD (2012)
Mário P. Véstias, Horácio C. Neto
Revisiting the Newton-Raphson Iterative Method for Decimal Division. FPL (2011)
Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
Run-Time Reconfigurable Array Using Magnetic RAM. DSD (2009)
Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias
Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. DSD (2009)
Horácio C. Neto, Mário P. Véstias
Decimal multiplier on FPGA using embedded binary multipliers. FPL (2008)
Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto
Multiplier-based double precision floating point divider according to the IEEE-754 standard. ARC (2008)
Mário P. Véstias, Horácio C. Neto
Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. FPL (2007)
Mário P. Véstias, Horácio C. Neto
Area/Performance Improvement of NoC Architectures. ARC (2006)
Mário P. Véstias, Horácio C. Neto
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. FPL (2006)
Mário P. Véstias, Horácio C. Neto
Area and performance optimization of a generic network-on-chip architecture. SBCCI (2006)
Mário P. Véstias, Horácio C. Neto
Co-synthesis of a configurable SoC platform based on a network on chip architecture. ASP-DAC (2006)
Mário P. Véstias, Horácio C. Neto
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. SBCCI (2003)
Mário P. Véstias, Horácio C. Neto
System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. IEEE International Workshop on Rapid System Prototyping (2002)