Sliding block Viterbi decoders in FPGA.
Mário P. VéstiasHorácio C. NetoHelena SarmentoPublished in: FPL (2012)
Keyphrases
- power reduction
- decoding algorithm
- hidden markov models
- hardware implementation
- field programmable gate array
- block wise
- sliding window
- signal processing
- real time image processing
- high speed
- digital signal
- power consumption
- fpga implementation
- verilog hdl
- real time
- block size
- block matching
- fixed size
- parallel architecture
- software implementation