Decimal multiplier on FPGA using embedded binary multipliers.

Horácio C. Neto Mário P. Véstias

Published in: FPL (2008)

Keyphrases

floating point
hardware implementation
embedded systems
field programmable gate array
high speed
signal processing
hw sw
non binary
hardware architecture
software implementation
database
low cost
fixed point
dedicated hardware
hardware design
verilog hdl
multi valued
multiscale
real time