Login / Signup

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA.

Wilson JoséAna Rita SilvaHorácio C. NetoMário P. Véstias
Published in: FPL (2014)
Keyphrases
  • efficient implementation
  • hardware implementation
  • active set
  • floating point
  • efficient processing
  • real time
  • database systems
  • information systems
  • low cost
  • signal processing
  • highly parallel