Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA.

Tiago Rodrigues Mário P. Véstias

Published in: DSD (2015)

Keyphrases

fpga implementation
dynamic reconfiguration
hardware implementation
decoding process
field programmable gate array
image compression
compression algorithm
software systems
low complexity
coded images
real time
artificial intelligence
motion estimation
image coding