José Monteiro

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 19

Top Venues

Publications

Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
A Fast Monte Carlo Algorithm for Evaluating Matrix Functions with Application in Complex Networks. J. Sci. Comput. 99 (2) (2024)
Inês A. Ferreira, Juan A. Acebrón, José Monteiro
Parallelization Strategies for the Randomized Kaczmarz Algorithm on Large-Scale Dense Systems. CoRR (2024)
Inês A. Ferreira, Juan A. Acebrón, José Monteiro
Survey of a Class of Iterative Row-Action Methods: The Kaczmarz Method. CoRR (2024)
Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
A stochastic method for solving time-fractional differential equations. Comput. Math. Appl. 159 (2024)
Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
A Fast Monte Carlo algorithm for evaluating matrix functions with application in complex networks. CoRR (2023)
Leonardo L. de Oliveira, Gabriel H. Eisenkraemer, Everton Alceu Carara, João B. Martins, José Monteiro
Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations. ACM Trans. Sens. Networks 19 (2) (2023)
Filipe Magalhães, José Monteiro, Juan A. Acebrón, José R. Herrero
A distributed Monte Carlo based linear algebra solver applied to the analysis of large complex networks. Future Gener. Comput. Syst. 127 (2022)
Orestis Korakitis, Simon Garcia de Gonzalo, Nicolas Guidotti, João Barreto, José Monteiro, Antonio J. Peña
OmpSs-2 and OpenACC Interoperation. WACCPD@SC (2022)
Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. 14 (5) (2022)
Miguel Marques, Ilia Kuzmin, João Barreto, José Monteiro, Rodrigo Rodrigues
Dynamic Page Placement on Real Persistent Memory Systems. CoRR (2021)
Nicolas Guidotti, Pedro Ceyrat, João Barreto, José Monteiro, Rodrigo Rodrigues, Ricardo Fonseca, Xavier Martorell, Antonio J. Peña
Particle-In-Cell Simulation using Asynchronous Tasking. CoRR (2021)
Nicolas Guidotti, Pedro Ceyrat, João Barreto, José Monteiro, Rodrigo Rodrigues, Ricardo Fonseca, Xavier Martorell, Antonio J. Peña
Particle-In-Cell Simulation Using Asynchronous Tasking. Euro-Par (2021)
Ahmed Liacha, Abdelkrim Kamel Oudjida, Mohammed Bakiri, José Monteiro, Paulo F. Flores
recoding with common subexpression elimination for multiple constant multiplication. IET Circuits Devices Syst. 14 (7) (2020)
Rafael Santos, João Afonso, José Monteiro
Short-circuit Analysis using a Parallel QBF Solver. DCIS (2020)
Juan A. Acebrón, José R. Herrero, José Monteiro
A highly parallel algorithm for computing the action of a matrix exponential on a vector based on a multilevel Monte Carlo method. Comput. Math. Appl. 79 (12) (2020)
João Afonso, José Monteiro
Analysis of short-circuit conditions in logic circuits. DATE (2017)
Ahmed Liacha, Abdelkrim Kamel Oudjida, Farid Ferguene, José Monteiro, Paulo F. Flores
algorithm for single constant multiplication. NEWCAS (2017)
Levent Aksoy, Paulo F. Flores, José Monteiro
A novel method for the approximation of multiplierless constant matrix vector multiplication. EURASIP J. Embed. Syst. 2016 (2016)
Nuno P. Lopes, José Monteiro
Automatic equivalence checking of programs with uninterpreted functions and integer arithmetic. Int. J. Softw. Tools Technol. Transf. 18 (4) (2016)
Diogo Brito, Taimur Gibran Rabuske, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
Quaternary Logic Lookup Table in Standard CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Levent Aksoy, Paulo F. Flores, José Monteiro
A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication. EUC (2015)
Levent Aksoy, Paulo F. Flores, José Monteiro
Approximation of multiple constant multiplications using minimum look-up tables on FPGA. ISCAS (2015)
Levent Aksoy, Paulo F. Flores, José Monteiro
Exact and Approximate Algorithms for the Filter Design Optimization Problem. IEEE Trans. Signal Process. 63 (1) (2015)
Levent Aksoy, Paulo F. Flores, José Monteiro
Optimization of design complexity in time-multiplexed constant multiplications. DATE (2014)
Levent Aksoy, Paulo F. Flores, José Monteiro
Multiplierless Design of Folded DSP Blocks. ACM Trans. Design Autom. Electr. Syst. 20 (1) (2014)
Nuno P. Lopes, José Monteiro
Weakest Precondition Synthesis for Compiler Optimizations. VMCAI (2014)
Levent Aksoy, Paulo F. Flores, José Monteiro
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. ICCD (2014)
Levent Aksoy, Paulo F. Flores, José Monteiro
A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. Circuits Syst. Signal Process. 33 (6) (2014)
Levent Aksoy, Paulo F. Flores, José Monteiro
ECHO: A novel method for the multiplierless design of constant array vector multiplication. ISCAS (2014)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Exploration of tradeoffs in the design of integer cosine transforms for image compression. ECCTD (2013)
Diogo Brito, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
Standard CMOS voltage-mode QLUT using a clock boosting technique. NEWCAS (2013)
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Nuno P. Lopes, José Monteiro
Automatic Equivalence Checking of UF+IA Programs. SPIN (2013)
Levent Aksoy, Paulo F. Flores, José Monteiro
SIREN: a depth-first search algorithm for the filter design optimization problem. ACM Great Lakes Symposium on VLSI (2013)
Levent Aksoy, Paulo F. Flores, José Monteiro
Towards the least complex time-multiplexed constant multiplication. VLSI-SoC (2013)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. Design Autom. Electr. Syst. 17 (1) (2012)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Multiple tunable constant multiplications: Algorithms and applications. ICCAD (2012)
Diogo Brito, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
Design and characterization of a QLUT in a standard CMOS process. ICECS (2012)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Design of low-complexity digital finite impulse response filters on FPGAs. DATE (2012)
João Bispo, João M. P. Cardoso, José Monteiro
Hardware pipelining of runtime-detected loops. SBCCI (2012)
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integr. 45 (3) (2012)
Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis
Efficient area and power multiplication part of FFT based on twiddle factor decomposition. ICECS (2012)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Finding the optimal tradeoff between area and delay in multiple constant multiplications. Microprocess. Microsystems 35 (8) (2011)
Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electron. 7 (2) (2011)
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS (2011)
Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. ICECS (2011)
Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Multiplierless Design of Linear DSP Transforms. VLSI-SoC (Selected Papers) (2011)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Design of low-power multiple constant multiplications using low-complexity minimum depth operations. ACM Great Lakes Symposium on VLSI (2011)
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI (2011)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC (2011)
Leonardo L. de Oliveira, Gustavo Fernando Dessbesell, João B. Martins, José Monteiro
Hardware implementation of a centroid-based localization algorithm for mobile sensor networks. ISCAS (2011)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Optimization of gate-level area in high throughput Multiple Constant Multiplications. ECCTD (2011)
Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS (2010)
Leonardo Londero de Oliveira, João Baptista dos Santos Martins, Gustavo Fernando Dessbesell, José Monteiro
CentroidM: a centroid-based localization algorithm for mobile sensor networks. SBCCI (2010)
Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, José Monteiro
Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC (2010)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD (2010)
Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro
A new quaternary FPGA based on a voltage-mode multi-valued circuit. DATE (2010)
Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. PATMOS (2010)
Nuno P. Lopes, Levent Aksoy, Vasco M. Manquinho, José Monteiro
Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability CoRR (2010)
Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro
Voltage-mode quaternary FPGAs: An evaluation of interconnections. ISCAS (2010)
António Gusmão, Luís Miguel Silveira, José Monteiro
Power Macro-Modeling Using an Iterative LS-SVM Method. VLSI-SoC (2009)
António Gusmão, L. Miguel Silveira, José Monteiro
Parameter tuning in SVM-based power macro-modeling. ISQED (2009)
Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (6) (2008)
Eduardo A. C. da Costa, José Monteiro, Sergio Bampi
operands. Integr. 40 (2) (2007)
Levent Aksoy, Ece Olcay Günes, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. SiPS (2007)
Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC (2007)
Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Minimum number of operations under a general number representation for digital filter synthesis. ECCTD (2007)
Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. ICECS (2006)
Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC (2006)
Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. SBCCI (2006)
Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
hybrid array multiplier using carry save adder format. SBCCI (2005)
Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. VLSI-SoC (2005)
Paulo F. Flores, José Monteiro, Eduardo A. C. da Costa
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. ICCAD (2005)
Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
Maximal sharing of partial terms in MCM under minimal signed digit representation. ECCTD (2005)
José C. Costa, Luís Miguel Silveira, Srinivas Devadas, José Monteiro
Power Estimation Using Probability Polynomials. Des. Autom. Embed. Syst. 9 (1) (2004)
Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
A New Pipelined Array Architecture for Signed Multiplication. SBCCI (2003)
Eduardo Costa, Sergio Bampi, José Monteiro
A New Architecture for 2's Complement Gray Encoded Array Multiplier. SBCCI (2002)
Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
A New Architecture for Signed Radix-2m Pure Array Multipliers. ICCD (2002)
Eduardo Costa, Sergio Bampi, José Monteiro
Power Efficient Arithmetic Operand Encoding. SBCCI (2001)
João Portela, José Monteiro
Power Optimized Viterbi Decoder Implementation through Architectural Transforms. SBCCI (2001)
José C. Costa, Srinivas Devadas, José Monteiro
Observability Analysis of Embedded Software for Coverage-Directed Validation. ICCAD (2000)
Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro
Probabilistic Bottom-Up RTL Power Estimation. ISQED (2000)
Antônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José Monteiro
Integrating Dynamic Power Management in the Design Flow. VLSI (1999)
Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro, João P. Marques Silva
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design (1999)
Srinivas Devadas, Sharad Malik, José Monteiro, Luciano Lavagno
CAD Techniques for Embedded System Design. VLSI Design (1999)
José C. Costa, José Monteiro, L. Miguel Silveira, Srinivas Devadas
A probabilistic approach for RT-level power modeling. ICECS (1999)
José Monteiro, Srinivas Devadas
Power Estimation Under User-Specified Input Sequences and Programs. Integr. Comput. Aided Eng. 5 (2) (1998)
José Monteiro, Srinivas Devadas, Abhijit Ghosh
Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (3) (1998)
José Rufino, Nuno Pedrosa, José Monteiro, Paulo Veríssimo, Guilherme Arroz
Hardware support for CAN fault-tolerant communication. ICECS (1998)
José Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (1) (1997)
Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. Very Large Scale Integr. Syst. 4 (4) (1996)
José Monteiro, Srinivas Devadas
Techniques for power estimation and optimization at the logic level: A survey. J. VLSI Signal Process. 13 (2-3) (1996)
José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
Scheduling Techniques to Enable Power Management. DAC (1996)
Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
Power estimation methods for sequential logic circuits. IEEE Trans. Very Large Scale Integr. Syst. 3 (3) (1995)
José Monteiro, Srinivas Devadas
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. ISLPD (1995)
José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI (1995)
Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
Precomputation-based sequential logic optimization for low power. ICCAD (1994)
José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto
Bitwise Encoding of Finite State Machines. VLSI Design (1994)
José Monteiro, Srinivas Devadas, Bill Lin
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. DAC (1994)
Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. 2 (4) (1994)

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Publication Activity (10 Years)

Top Topics

Top Venues

José Monteiro