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Sequential logic optimization for low power using input-disabling precomputation architectures.
José Monteiro
Srinivas Devadas
Abhijit Ghosh
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1998)
Keyphrases
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low power
logic circuits
power consumption
high speed
low cost
delay insensitive
single chip
high power
digital signal processing
wireless transmission
vlsi circuits
image sensor
digital circuits
mixed signal
signal processing
cmos technology
vlsi architecture
low power consumption
energy dissipation
ultra low power