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Estimation of average switching activity in combinational logic circuits using symbolic simulation.
José Monteiro
Srinivas Devadas
Abhijit Ghosh
Kurt Keutzer
Jacob K. White
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1997)
Keyphrases
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logic circuits
tunnel diode
low power
functional decomposition
gate array
logic synthesis
low cost
estimation error
neural network
estimation algorithm
power consumption
power dissipation
interconnection networks
dynamical systems
load balancing
high speed
case study