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Sidinei Ghissoni
Publication Activity (10 Years)
Years Active: 2009-2018
Publications (10 Years): 2
Top Topics
Fir Filters
Fourier Transform
Factors That Affect
Lightweight
Top Venues
ICECS
SBCCI
VLSI-SoC
PATMOS
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Publications
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João G. Nizer Rahmeier
,
Eduardo A. C. da Costa
,
Alessandro Girardi
,
Sidinei Ghissoni
Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication.
SBCCI
(2018)
Sidinei Ghissoni
,
Eduardo Costa
,
Ricardo Reis
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs.
PATMOS
(2015)
Sidinei Ghissoni
,
Eduardo A. C. da Costa
,
Angelo Goncalves da Luz
Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors.
VLSI-SoC
(2014)
Angelo Goncalves da Luz
,
Eduardo A. C. da Costa
,
Sidinei Ghissoni
Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms.
LASCAS
(2013)
João G. Nizer Rahmeier
,
Angelo G. da Luz
,
Eduardo A. C. da Costa
,
Sidinei Ghissoni
Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm.
ICECS
(2013)
Sidinei Ghissoni
,
Eduardo Costa
,
José Monteiro
,
Ricardo Reis
Efficient area and power multiplication part of FFT based on twiddle factor decomposition.
ICECS
(2012)
Sidinei Ghissoni
,
Eduardo Costa
,
José Monteiro
,
Ricardo Reis
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.
ICECS
(2011)
Sidinei Ghissoni
,
Eduardo Costa
,
Cristiano Lazzari
,
José Monteiro
,
Levent Aksoy
,
Ricardo Reis
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.
ICECS
(2010)
Sidinei Ghissoni
,
João Baptista dos Santos Martins
,
Ricardo Augusto da Luz Reis
,
José C. Monteiro
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates.
PATMOS
(2009)