Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor.
C. J. TavaresC. BungardeanG. M. MatosJosé T. de SousaPublished in: FPL (2004)
Keyphrases
- parallel architecture
- high speed
- single chip
- embedded processors
- boolean formula
- gate array
- sat solving
- np complete problems
- stochastic local search
- augmented reality
- hardware implementation
- virtual environment
- sat instances
- digital signal
- parallel processing
- satisfiability testing
- fpga device
- low cost
- field programmable gate array
- search algorithm
- graph coloring
- low power
- propositional satisfiability
- clause learning
- variable ordering
- phase transition
- davis putnam
- signal processing
- virtual world
- np complete
- davis putnam logemann loveland
- dynamic random access memory
- efficient implementation
- satisfiability problem
- embedded systems
- sat problem