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Raul Chipana
Publication Activity (10 Years)
Years Active: 2010-2014
Publications (10 Years): 0
Top Topics
Duty Cycle
Quantitative Analysis
Top Venues
ISVLSI
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Publications
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Raul Chipana
,
Fernanda Gusmão de Lima Kastensmidt
SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies.
ISVLSI
(2014)
Raul Chipana
,
Eduardo Chielle
,
Fernanda Lima Kastensmidt
,
Jorge L. Tonfat
,
Ricardo Reis
Soft-Error Probability Due to SET in Clock Tree Networks.
ISVLSI
(2012)
Raul Chipana
,
Fernanda Lima Kastensmidt
,
Jorge L. Tonfat
,
Ricardo Reis
SET susceptibility estimation of clock tree networks from layout extraction.
LATW
(2012)
Costas Argyrides
,
Raul Chipana
,
Fabian Vargas
,
Dhiraj K. Pradhan
Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction.
IEEE Trans. Reliab.
60 (3) (2011)
Jimmy Tarrillo
,
Raul Chipana
,
Eduardo Chielle
,
Fernanda Lima Kastensmidt
Designing and analyzing a SpaceWire router IP for soft errors detection.
LATW
(2011)
Raul Chipana
,
Letícia Maria Veiras Bolzani
,
Fabian Vargas
,
Jorge Semião
,
Juan J. Rodríguez-Andina
,
Isabel C. Teixeira
,
João Paulo Teixeira
Investigating the Use of BICS to detect resistive-open defects in SRAMs.
IOLTS
(2010)
Raul Chipana
,
Letícia Maria Veiras Bolzani
,
Fabian Vargas
BICS-based March test for resistive-open defect detection in SRAMs.
LATW
(2010)