Jaume Segura

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 17

Top Topics

Database Manager

Top Venues

Microelectron. Reliab.

Publications

Rafel Perelló-Roig, Salvador Barceló, Jaume Verd, Sebastià A. Bota, Jaume Segura
A 164-dBΩ Transimpedance Amplifier for Monolithic CMOS-MEMS Oscillators in Biosensing Applications. IEEE Access 12 (2024)
Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. J. Electron. Test. 40 (1) (2024)
Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastia Bota, Jaume Segura
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. CoRR (2024)
Sebastià A. Bota, Salvador Barcelo, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura
A Compact Double-Exponential Circuit for Single Event Transient Emulation. DCIS (2023)
Rafel Perelló-Roig, Francisca Orvay, Ivan de Paúl, Jaume Verd, Sebastià A. Bota, Jaume Segura
Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring. IEEE SENSORS (2022)
Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations. LATS (2022)
Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura
Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing. Sensors 20 (17) (2020)
Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Daniel Malagón-Periánez, Jaume Segura, Sebastià A. Bota
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. IEEE Trans. Emerg. Top. Comput. 7 (3) (2019)
Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura
Frequency Fluctuations in CMOS-MEMS Oscillators: Towards the Thermomechanical Limit. ISCAS (2018)
Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura, Jaume Verd
Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. ISCAS (2018)
Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura
Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators. Sensors 18 (9) (2018)
Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Gabriel Torrens, Sebastià A. Bota, Jaume Segura, Francesc Moll, Antonio Rubio
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells. SMACD (2017)
Jaume Segura
Integrated microelectromechanical systems in the More than Moore era. DTIS (2017)
Sebastià A. Bota, Jaume Verd, Joan Barceló, Xavier Gili, Bartomeu Alorda, Gabriel Torrens, Carol de Benito, Jaume Segura
Cantilever NEMS relay-based SRAM devices for enhanced reliability. DTIS (2017)
Daniel Malagón, Sebastià A. Bota, Gabriel Torrens, Xavier Gili, Javier Praena, B. Fernández, Miguel Macías, Jose Manuel Quesada Molina, Carlos Guerrero Sanchez, María del Carmen Jiménez-Ramos, Javier García López, José Luis Merino, Jaume Segura
Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources. Microelectron. Reliab. 78 (2017)
Joan Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura, Jaume Verd
Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective. Commun. Nonlinear Sci. Numer. Simul. 30 (Issues) (2016)
Hector Villacorta, Jaume Segura, Víctor H. Champac
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. J. Electron. Test. 32 (3) (2016)
Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura, Víctor H. Champac
and body bias conditions for testing bridge defects in the presence of process variations. Microelectron. J. 46 (5) (2015)
Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura, Víctor H. Champac
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. LATS (2015)
Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. 54 (11) (2014)
Hector Villacorta, Jaume Segura, Sebastià A. Bota, Víctor H. Champac
Analysis of fin height on FinFET SRAM cell hardening. MWSCAS (2014)
Salvador Barcelo, Xavier Gili, Sebastià A. Bota, Jaume Segura
Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
José Luis Merino, Sebastià Antoni Bota, Rodrigo Picos, Jaume Segura
Alternate characterization technique for static random-access memory static noise margin determination. Int. J. Circuit Theory Appl. 41 (10) (2013)
Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura, Roberto Gómez
Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. IEEE Des. Test 30 (6) (2013)
Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura
Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. LATW (2013)
Hector Villacorta, Víctor H. Champac, Sebastià A. Bota, Jaume Segura
and body bias in a delay based test. Microelectron. Reliab. 52 (11) (2012)
Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barcelo, Roberto Gómez, Chuck Hawkins, Jaume Segura
Testing of Stuck-Open Faults in Nanometer Technologies. IEEE Des. Test Comput. 29 (4) (2012)
Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
8T vs. 6T SRAM cell radiation robustness: A comparative analysis. Microelectron. Reliab. 51 (2) (2011)
Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. DATE (2011)
Salvador Barcelo, Xavier Gili, Sebastià A. Bota, Jaume Segura
An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation. DATE (2011)
Sebastià A. Bota, Gabriel Torrens, Bartomeu Alorda, Jaume Verd, Jaume Segura
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. IOLTS (2010)
Hector Villacorta, Víctor H. Champac, Chuck Hawkins, Jaume Segura
Reliability analysis of small delay defects in vias located in signal paths. LATW (2010)
Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. DATE (2010)
Gabriel Torrens, Bartomeu Alorda, Salvador Barcelo, José Luis Rosselló, Sebastià A. Bota, Jaume Segura
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. Circuits Syst. II Express Briefs (4) (2010)
Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS (2009)
Roberto Gómez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
A modern look at the CMOS stuck-open fault. LATW (2009)
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura
Using stochastic logic for efficient pattern recognition analysis. IJCNN (2008)
Bartomeu Alorda, Ivan de Paúl, Jaume Segura
Charge-based testing BIST for embedded memories. IET Comput. Digit. Tech. 1 (5) (2007)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs CoRR (2007)
X. Cano, Sebastià A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura, Lluís Garrido
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. IOLTS (2007)
José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. DATE (2007)
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs CoRR (2007)
Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura
Impact of Thermal Gradients on Clock Skew and Testing. IEEE Des. Test Comput. 23 (5) (2006)
Jaume Segura
CMOS Testing at the End of the Roadmap: Challenges and Opportunities. DDECS (2006)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. VTS (2006)
José Luis Rosselló, Jaume Segura
A compact model to identify delay faults due to crosstalk. DATE (2006)
José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
Leakage Power Characterization Considering Process Variations. PATMOS (2006)
José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN (2006)
José Luis Rosselló, Sebastià A. Bota, Jaume Segura
Compact Static Power Model of Complex CMOS Gates. PATMOS (2005)
Bartomeu Alorda, Sebastià A. Bota, Jaume Segura
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. IOLTS (2005)
Chuck Hawkins, Jaume Segura
The anatomy of nanometer timing failures. ETS (2005)
José Luis Rosselló, Carol de Benito, Jaume Segura
A compact gate-level energy and delay model of dynamic CMOS gates. IEEE Trans. Circuits Syst. II Express Briefs (10) (2005)
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE (2005)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. DATE (2005)
Bartomeu Alorda, Vincent Canals, Jaume Segura
A Two-Level Power-Grid Model for Transient Current Testing Evaluation. J. Electron. Test. 20 (5) (2004)
Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura
A BIST-based Charge Analysis for Embedded Memories. IOLTS (2004)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ITC (2004)
José Luis Rosselló, Jaume Segura
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. DATE (2004)
Josep Altet, Antonio J. Rubio, José Luis Rosselló, Jaume Segura
Structural RFIC device testing through built-in thermal monitoring. IEEE Commun. Mag. 41 (9) (2003)
Charles F. Hawkins, Ali Keshavarzi, Jaume Segura
A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. DFT (2003)
Bartomeu Alorda, Brad Bloechel, Ali Keshavarzi, Jaume Segura
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. ITC (2003)
Bartomeu Alorda, Jaume Segura
An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. IOLTS (2003)
Charles F. Hawkins, Ali Keshavarzi, Jaume Segura
CMOS IC nanometer technology failure mechanisms. CICC (2003)
Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern, Jaume Segura, Miquel Roca, Eugenio García
A BICS for CMOS OpAmps by Monitoring the Supply Current Peak. J. Electron. Test. 19 (5) (2003)
José Luis Rosselló, Jaume Segura
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. PATMOS (2003)
José Luis Rosselló, Jaume Segura
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. PATMOS (2002)
Chuck Hawkins, Jaume Segura
GHz Testing and Its Fuzzy Targets. ITC (2002)
Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura
Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. ITC (2002)
Jaume Segura, Peter C. Maxwell
Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. IEEE Des. Test Comput. 19 (5) (2002)
Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins
Parametric Failures in CMOS ICs - A Defect-Based Analysis. ITC (2002)
José Luis Rosselló, Jaume Segura
Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Bartomeu Alorda, André Ivanov, Jaume Segura
An Off-Chip Sensor Circuit for On-Line Transient Current Testing. IOLTW (2002)
Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García
A BICS for CMOS Opamps by Monitoring the Supply Current Peak. IOLTW (2002)
Jaume Segura, Vivek De, Ali Keshavarzi
Challenges in Nanometric Technology Scaling: Trends and Projections. VTS (2002)
Swarup Bhunia, Kaushik Roy, Jaume Segura
A novel wavelet transform based transient current analysis for fault detection and localization. DAC (2002)
José Luis Rosselló, Jaume Segura
Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. ICCAD (2001)
Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. VTS (2001)
Rodrigo Picos, J. Colom, Miquel Roca, Eugeni Isern, Jaume Segura, Oscar Calvo, Eugenio García-Moreno
Transient Current Monitoring Using a Current-to-Frequency Converter. LATW (2000)
Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugeni García-Moreno
Experimental Results on BIC Sensors for Transient Current Testing. J. Electron. Test. 16 (3) (2000)
Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. IOLTW (2000)
Eugeni Isern, Miquel Roca, Jaume Segura
Analyzing the Need for ATPG Targeting GOS Defects. VTS (1999)
Charles F. Hawkins, Jaume Segura, Jerry M. Soden, Ted Dellin
Test and Reliability: Partners in IC Manufacturing, Part 2. IEEE Des. Test Comput. 16 (4) (1999)
Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Enrique García-Moreno
Experimental results on BIC sensors for transient current testing. ETW (1999)
Charles F. Hawkins, Jaume Segura
Test and Reliability: Partners in IC Manufacturing, Part 1. IEEE Des. Test Comput. 16 (3) (1999)
Jaume Segura, José Luis Rosselló, J. Morra, H. Sigg
A variable threshold voltage inverter for CMOS programmable logic circuits. IEEE J. Solid State Circuits 33 (8) (1998)
Eugeni García-Moreno, Benjamín Iñíguez, Miquel Roca, Jaume Segura, Eugeni Isern
Clocked Dosimeter Compatible with Digital CMOS Technology. J. Electron. Test. 12 (1-2) (1998)
O. Calvo, M. González, C. Romero, Enrique García-Moreno, Eugeni Isern, Miquel Roca, Jaume Segura
Integrated Cmos Linear Dosimeter. SBCCI (1998)
Jaume Segura, Antonio Rubio
A detailed analysis of CMOS SRAM's with gate oxide short defects. IEEE J. Solid State Circuits 32 (10) (1997)
Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. J. Electron. Test. 8 (3) (1996)
Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. ITC (1995)
Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura
A built-in quiescent current monitor for CMOS VLSI circuits. ED&TC (1995)