A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors.
Gabriel TorrensBartomeu AlordaCristian CarmonaDaniel Malagón-PeriánezJaume SeguraSebastià A. BotaPublished in: IEEE Trans. Emerg. Top. Comput. (2019)
Keyphrases
- multi channel
- cmos technology
- power consumption
- low power
- nm technology
- low voltage
- metal oxide semiconductor
- parallel processing
- low cost
- circuit design
- power dissipation
- high speed
- power management
- image sensor
- single chip
- cost effective
- digital signal processing
- energy consumption
- random access memory
- computational complexity